Memory cells

Active solid-state devices (e.g. – transistors – solid-state diode – Bulk effect device – Bulk effect switching in amorphous material

Reexamination Certificate

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Details

C257S002000, C257S003000, C257S005000, C257S054000, C257S095000, C257SE21090, C257SE21413, C257SE27004, C257SE45002, C257SE45003, C257SE47001, C365S106000, C365S163000, C438S095000, C438S097000, C438S102000, C438S104000

Reexamination Certificate

active

08080817

ABSTRACT:
In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the channel region from the source region. The channel region has phase change material adjacent the drain region. In some embodiments, the phase change material may be adjacent both the source region and the drain region. Some embodiments include methods of programming a memory cell that has phase change material adjacent a drain region. An inversion layer is formed within the channel region adjacent the gate dielectric, with the inversion layer having a pinch-off region within the phase change material adjacent the drain region. Hot carriers (for instance, electrons) within the pinch-off region are utilized to change a phase within the phase change material.

REFERENCES:
patent: 7015076 (2006-03-01), Chan et al.
patent: 7494841 (2009-02-01), Mitzi et al.
patent: 2005/0111252 (2005-05-01), Bednorz et al.
patent: 2006/0197082 (2006-09-01), Cho et al.
patent: 2008/0049490 (2008-02-01), Hosaka et al.
patent: 2008/0083924 (2008-04-01), Song et al.

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