Memory cells

Details Memory cells Memory cells

1977-12-16

1978-07-25

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307279, 307288, 365156, 365181, 365184, 365185, G11C 1140, H03K 3286, H03K 3353

Patent

active

041031857

ABSTRACT:
Transistor memory cells which may be operated in both the erasable "read only" and the "random access" modes. Each cell includes a plurality of MOS transistors interconnected to permit random access storage and at least two MNOS transistors. The latter may be set, one to one threshold level and the other to a second threshold level to represent read only storage of a logic 1, and the threshold levels may be reversed to represent read only storage of a logic 0. The MOS transistors may be randomly accessed both for read and write independently of what the MNOS transistors are storing.

REFERENCES:
patent: 3555307 (1971-01-01), Hujita
patent: 3629612 (1971-12-01), Harbert
patent: 3636530 (1972-01-01), Mark et al.
patent: 3651492 (1972-03-01), Lockwood
patent: 3660827 (1972-05-01), Tickle
patent: 3676717 (1972-07-01), Lockwood
patent: 3836894 (1974-09-01), Cricchi
patent: 3845327 (1974-10-01), Cricchi
patent: 3895360 (1975-07-01), Cricchi et al.
patent: 3936811 (1976-02-01), Horninger
patent: 3950737 (1976-04-01), Uchida et al.
Frohman-Bentchkowsky, Proceedings of the IEEE; vol. 58, No. 8, pp. 1207-1219; 8/1970.

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