Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor
Reexamination Certificate
2006-12-05
2006-12-05
Ngo, Ngan V (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Combined with field effect transistor
C257S146000, C257SE29211, C257SE29216
Reexamination Certificate
active
07145186
ABSTRACT:
One aspect of this disclosure relates to a memory cell. Various memory cell embodiments include an isolated semiconductor region separated from a bulk semiconductor region, an access transistor and a vertically-oriented thyristor formed in a trench extending between the isolated and bulk semiconductor regions. The access transistor includes a first diffusion region connected to a bit line, a second diffusion region to function as a storage node, a floating body region, and a gate separated from the floating body region by a transistor gate insulator. The isolated semiconductor region includes the first and second diffusion regions and the floating body region of the access transistor. The thyristor has a first end in contact with the bulk semiconductor region and a second end in contact with the storage node. The thyristor is insulated from the floating body region by a thyristor gate insulator. Other aspects and embodiments are provided herein.
REFERENCES:
patent: 3918033 (1975-11-01), Case et al.
patent: 3964085 (1976-06-01), Kahng et al.
patent: 3978577 (1976-09-01), Bhattacharyya et al.
patent: 4488262 (1984-12-01), Basire et al.
patent: 4754310 (1988-06-01), Coe
patent: 4791604 (1988-12-01), Lienau et al.
patent: 4829482 (1989-05-01), Owen
patent: 4870470 (1989-09-01), Bass, Jr. et al.
patent: 5043946 (1991-08-01), Yamauchi et al.
patent: 5382814 (1995-01-01), Ashley et al.
patent: 5396454 (1995-03-01), Nowak
patent: 5488243 (1996-01-01), Tsuruta et al.
patent: 5557569 (1996-09-01), Smayling et al.
patent: 5621683 (1997-04-01), Young
patent: 5627779 (1997-05-01), Odake et al.
patent: 5801993 (1998-09-01), Choi
patent: 5814853 (1998-09-01), Chen
patent: 5963476 (1999-10-01), Hung et al.
patent: 5981335 (1999-11-01), Chi
patent: 6104045 (2000-08-01), Forbes et al.
patent: 6118152 (2000-09-01), Yamaguchi et al.
patent: 6201734 (2001-03-01), Sansbury et al.
patent: 6243296 (2001-06-01), Sansbury
patent: 6248626 (2001-06-01), Kumar et al.
patent: 6294427 (2001-09-01), Furuhata et al.
patent: 6462359 (2002-10-01), Nemati et al.
patent: 6545297 (2003-04-01), Noble et al.
patent: 6574143 (2003-06-01), Nakazato
patent: 6600188 (2003-07-01), Jiang et al.
patent: 6611452 (2003-08-01), Han
patent: 6617651 (2003-09-01), Ohsawa
patent: 6638627 (2003-10-01), Potter
patent: 6653174 (2003-11-01), Cho et al.
patent: 6653175 (2003-11-01), Nemati et al.
patent: 6660616 (2003-12-01), Babcock et al.
patent: 6661042 (2003-12-01), Hsu
patent: 6888200 (2005-05-01), Bhattacharyya
patent: 6917078 (2005-07-01), Bhattacharyya
patent: 2002/0048190 (2002-04-01), King
patent: 2002/0105023 (2002-08-01), Kuo et al.
patent: 2003/0042534 (2003-03-01), Bhattacharyya et al.
patent: 2003/0072126 (2003-04-01), Bhattacharyya
patent: 2003/0089942 (2003-05-01), Bhattacharyya
patent: 2003/0151948 (2003-08-01), Bhattacharyya et al.
patent: 2003/0160277 (2003-08-01), Bhattacharyya et al.
patent: 2004/0007734 (2004-01-01), Kato et al.
patent: 2004/0014304 (2004-01-01), Bhattacharyya
patent: 2004/0026728 (2004-02-01), Yoshida et al.
patent: 2004/0041206 (2004-03-01), Bhattacharyya
patent: 2005/0001232 (2005-01-01), Bhattacharyya
patent: 2005/0026353 (2005-02-01), Bhattacharya
patent: 2005/0026354 (2005-02-01), Bhattacharyya
patent: 2005/0263763 (2005-12-01), Bhattacharyya
patent: 61-166078 (1986-07-01), None
Bauer, F , et al., “Design aspects of MOS controlled thyristor elements”,International Electron Devices Meeting 1989. Technical Digest.(1989), 297-300.
Bhattacharyya, A. , “Physical & Electrical Characteristics of LPCVD Silicon Rich Nitride”,ECS Technical Digest, J. Electrochem. Soc.,131(11). 691 RDP, New Orleans, (1984), 469C.
Carter, R J., “Electrical Characterization of High-k Materials Prepared By Atomic Layer CVD”,IWGI,(2001), 94-99.
Chang, H R., et al., “MOS trench gate field-controlled thyristor”,Technical Digest—International Electron Devices Meeting,(1989), 293-296.
Choi, J D., et al., “A0.15 um NAND Flash Technology with ). 11 um2 cell Size for 1 Gbit Flash Memory”,IEDM Technical Digest,(2000), 767-770.
Fazan, P , et al., “Capacitor-Less 1-Transistor DRAM”,IEEE International SOI Conference,(2002), 10-13.
Frohman-Bentchkowsky, D , “An integrated metal-nitride-oxide-silicon (MNOS) memory”,Proceedings of the IEEE,57(6), (Jun. 1969), 1190-1192.
Han, Kwangseok , “Characteristics of P-Channel Si Nano-Crystal Memory”,IEDM Technical Digest, International Electron Devices Meeting,(Dec. 10-13, 2000), 309-312.
Jagar, S , “Single grain thin-film-transistor (TFT) with SOI CMOS performance formed by metal-induced-lateral-crystallization”,International Electron Devices Meeting 1999. Technical Digest,(1999), 293-6.
Kumar, M. J., “Lateral Schottky Rectifiers for Power Integrated Circuits”,International Workshop on the Physics of Semiconductor Devices,11th. 4746, Allied Publishers Ltd., New Delhi, India, (2002), 414-421.
Lai, S K., et al., “Comparison and trends in Today's dominant E2 Technologies”,IEDM Technical Digest,(1986), 580-583.
Nemati, F , et al., “A novel high density, low voltage SRAM cell with a vertical NDR device”,1998 Symposium on VLSI Technology Digest of Technical Papers,(1998), 66-7.
Nemati, F , et al., “A novel thyristor-based SRAM cell (T-RAM) for high-speed, low-voltage, giga-scale memories”,International Electron Devices Meeting 1999. Technical Digest,(1999), 283-6.
Ohsawa, T , et al., “Memory design using one-transistor gain cell on SOI”,IEEE International Solid-State Circuits Conference. Digest of Technical Papers,vol. 1, (2002), 452-455.
Okhonin, S , “A SOI capacitor-less 1T-DRAM concept”,2001 IEEE International SOI Conference. Proceedings, IEEE. 2001,(2000), 153-4.
Shinohe, T , et al., “Ultra-high di/dt 2500 V MOS assisted gate-triggered thyristors (MAGTs) for high repetition excimer laser system”,International Electron Devices Meeting 1989. Technical Digest,(1989), 301-4.
Sze, S. M., “Table 3: Measured Schottky Barrier Heights”,In: Physics of Semiconductor Devices,John Wiley & Sons, Inc., (1981), p. 291.
Tiwari, Sandip , “Volatile and Non-Volatile Memories in Silicon with Nano-Crystal Storage”,Int'l Electron Devices Meeting: Technical Digest,Washington, DC,(Dec. 1995), 521-524.
Van Meer, H , “Ultra-thin film fully-depleted SOI CMOS with raised G/S/D device architecture for sub-100 nm applications”,2001 IEEE International SOI Conference,(2001), 45-6.
Zhang, H. , “Atomic Layer Deposition of High Dielectric Constant Nanolaminates”,Journal of The Electrochemical Society,148(4), (Apr. 2001), F63-F66.
Ngo Ngan V
Schwegman Lundberg Woessner & Kluth P.A.
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