Memory cell with single-event-upset tolerance

Details Memory cell with single-event-upset tolerance Memory cell with single-event-upset tolerance

2007-01-03

2009-12-29

Hu, Shouxiang (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

C257S208000, C257SE27108, C257S903000, C365S154000

Reexamination Certificate

active

07638822

ABSTRACT:
A memory cell having a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value has an aspect ratio of at least 5:1. The high aspect ratio provides adequate spacing between nodes of the memory cell for SEU tolerance at small design technologies.

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