Memory cell with single bit line read back

Details Memory cell with single bit line read back Memory cell with single bit line read back

1994-11-30

1997-11-11

Fears, Terrell W.

Static information storage and retrieval

Addressing

365203, 36518901, G11C 1300

Patent

active

056871309

ABSTRACT:
The spatial light modulator (30) of the DMD type having associated memory cells (10) with a single bit line memory read back architecture (54). The memory cells (10) include a charge equalization switch (50) comprising a transistor connected across the bit lines (16,18) of the memory cell (10). This charge equalization transistor (50) is momentarily turned on (T.sub.3) to balance residual charge on the memory cell bit lines (16,18), after a write cycle (T.sub.2) but before the read cycle (T.sub.4). When the memory cell contents are subsequently read (T.sub.4), the memory cell contents will not change state. A single amplifier (54) is connected to one bit line for reading the memory cell contents. The single bit line (18) memory read back architecture provides a more efficient circuit layout to the spacing constraints required with DMDs, consumes less power than designs with a differential amplifier, and additionally, provides yield improvements.

REFERENCES:
patent: 5061049 (1991-10-01), Hornbeck
patent: 5079544 (1992-01-01), DeMond et al.
patent: 5105369 (1992-04-01), Nelson
patent: 5594701 (1997-01-01), Asaka et al.
U.S. application No. 08/002,627, Korner et al., filed Jan. 11, 1993.

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