Memory cell with latent image capabilities

Details Memory cell with latent image capabilities Memory cell with latent image capabilities

1984-02-27

1986-04-22

Moffitt, James W.

Static information storage and retrieval

Read only systems

With override

365154, 365 96, G11C 506, G11C 1140

Patent

active

045846693

ABSTRACT:
A CMOS circuit is disclosed which has a latent image feature for application in FET memory arrays for writable read only storage applications. A four device cross-coupled CMOS circuit is formed with minimum real estate area, so as to allow for wiring level programming into a preconditioned binary one or zero state. The preconditioned circuit will assume a preselected binary state when power is turned on. Thereafter, the circuit can be accessed for normal binary one and zero selective storage without a significant diminution in its operating characteristics, when compared with conventional CMOS cross-coupled storage circuits.

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Gonauser et al., "A Master Slice Design Concept Based on Master Cells in ESFI-SOS-CMOS Technology", Siemens Forsch.-u. Entwickl.-Ber. Bd. 5, #6, 1976, pp. 344-349.

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