Memory cell with known state on power up

Details Memory cell with known state on power up Memory cell with known state on power up

1991-05-24

1992-09-15

Popek, Joseph A.

Static information storage and retrieval

Read only systems

With override

365154, G11C 1140

Patent

active

051483904

ABSTRACT:
A five transistor memory cell that can be reliably read and written from a single data line. The cell includes two inverters and a pass transistor. The cell read/write circuitry includes an address supply voltage source which is maintained at a first level during write and at a second level during read, selected to reduce read disturbance. The memory cell read circuitry includes a circuit for precharging the cell data line prior to reading. The state of the memory cell is continuously available at output nodes to control other circuitry even during the read operation. Selective doping of the pull-up transistors of the inverters in the memory cell controls the initial state of the memory cell after the memory cell is powered up.

REFERENCES:
patent: 3493786 (1970-02-01), Ahrons et al.
patent: 4132904 (1979-01-01), Harari
patent: 4149268 (1979-04-01), Waters
patent: 4333166 (1982-06-01), Edwards
patent: 4342101 (1982-07-01), Edwards
patent: 4460978 (1984-07-01), Jiang et al.
patent: 4799194 (1989-01-01), Arakawa

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