Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1998-09-29
2001-03-27
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S238000
Reexamination Certificate
active
06207524
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a dynamic random access memory, and more particularly, to a memory cell that uses a stacked capacitor, for use in such a memory and to a method for making the stacked capacitor.
BACKGROUND OF THE INVENTION
A standard dynamic random access memory (DRAM) employs, as the memory cell that is formed in a large array in a silicon chip, a series combination of a switch, generally a MOSFET, and a storage capacitor in which a binary digit (bit) is stored as information for later recovery. In one form of DRAM, the storage capacitor is formed by a stack of layers over the top surface of the silicon chip with the MOSFET switch formed within a region near the top surface of the chip. A conductive plug typically provides a low resistance connection between a source/drain region of the MOSFET in the chip and the layer of the stack that serves as the lower plate (bottom electrode) of the storage capacitor.
To achieve high capacity in DRAMS it is important to make the cells small and to position them closely. It is accordingly important that the stacked capacitor in a DRAM use little surface space on the surface of the chip but still provide a sufficiently high capacitance to serve reliability as the storage node.
SUMMARY OF THE INVENTION
The present invention is a DRAM that comprises an improved stacked capacitor and a process for the manufacture of such a DRAM. As is known, generally the manufacture is largely done on a wafer scale and eventually the wafer is diced into a chip that will house one or more DRAMS. It will be convenient to discuss the processing primarily with respect to a portion of a chip that will house a single memory cell.
The essential elements of the improved capacitor for a memory cell are formed by first forming a contact hole in the dielectric layer that overlies the top surface of a portion of the silicon chip that houses a switching transistor. A contact hole is formed for each capacitor over the region of the switching transistor where the capacitor is to be connected. A conductive plug, typically of doped polysilicon, is then provided at a bottom portion of the contact hole to make a low resistance connection to such region of the transistor, such region corresponding to the storage node of the cell. Typically this is done by first filling the contact hole with a conductor and then removing the top portion of the fill. This leaves only a bottom plug portion. The empty top portion of the contact hole is then widened by etching. The wall of the widened trench is now coated with a layer of a conductor, advantageously platinum, to form a low resistance connection between the coating and the conductive plug. This conductive layer serves as the lower plate (bottom electrode) of the capacitor. When the conductive plug is of a material that needs to be prevented from diffusing into the conductor serving as the lower plate of the capacitor, as is the case with platinum, there should be interposed between the plug and the lower plate a layer of a material that will serve as a barrier to such diffusion. After the deposition of the conductive layer, the diffusion barrier and conductive layer are patterned to localize each in the interior of the widened trench for proper isolation. The conductive layer is then coated with a material of dielectric constant suitable for use as the capacitor dielectric. A layer of barium strontium titanate is presently preferred because its very high dielectric constant makes for an efficient capacitor dielectric. The dielectric layer in turn is coated with a conductive layer, also advantageously of platinum. This platinum layer serves as the upper plate (top electrode) of the capacitor. Of course, measures need be taken to avoid electric shorts between the top and bottom electrodes of the capacitor.
An advantage of this capacitor design is that the storage trench is essentially self-aligned so that its fabrication can be done with a reduced number of lithography steps. Another advantage of this capacitor is that it can readily be made with relatively thin layers of platinum as compared to the layers used in prior design. Platinum is advantageous because of both its favorable work function and its resistance to oxidation.
It is important that individual storage cells be isolated. Accordingly, it is important that the first layer and any diffusion barrier layer be patterned to avoid shorts as discussed above. However, the dielectric layer that serves as the capacitor dielectric and the conductive layer that serves as the upper plate of the capacitor can be extended over the chip to serve in the same roles in other cells of the memory cell array.
Viewed from one process aspect, the present invention is directed to a method for forming a memory cell including a transistor and a capacitor. The method comprises the steps of: forming in a semiconductor chip a transistor having first and second regions of one conductivity-type spaced apart by a region of the opposite conductivity-type along a top surface of said chip; forming a dielectric layer over a top surface of the chip; forming a contact hole with substantially vertical side walls in the dielectric layer by anisotropic etching for exposing a top surface portion of said second region of the transistor; filling the contact hole with a conductive fill for providing a low resistance connection to said second region; removing the top portion of the conductive fill of the contact hole for forming a recess in the conductive fill and exposing the dielectric layer in the contact hole; etching the exposed dielectric layer isotropically for widening the recess and enlarging the surface area of the contact hole in the dielectric layer; depositing a first conductive layer conformally over the enlarged surface area of the contact hole suitable for use as a lower plate of a storage capacitor; patterning this conductive layer for confining it essentially to the interior of the contact hole, depositing a layer of a material of high dielectric constant for covering the first conductive layer; and depositing a second conductive layer conformally over the last mentioned dielectric layer suitable for use as an upper plate of a capacitor that comprises electrically isolated upper and lower plates separated by the layer of high dielectric constant.
Viewed from an other process aspect, the present invention is directed to a method of forming a stacked capacitor on the top surface of a silicon wafer for use as a storage capacitor in series with a switching transistor formed in a top surface portion of the silicon wafer. The method comprises the steps of: forming a first dielectric layer over the top surface of the silicon wafer; forming a contact hole in the dielectric coating for exposing the portion of the silicon transistor to which the lower plate of the storage capacitor is to be electrically connected; partially filling the contact hole with doped polysilicon suitable for forming an electrical connection to said portion of the silicon transistor; widening the unfilled portion of the contact hole to a cup-shape for enlarging the surface area of the unfilled portion; forming a diffusion barrier conductive layer over the doped polysilicon; depositing conformally over the surface of the unfilled portion of the contact hole, a first conductive layer suitable for serving as said lower plate of the capacitor; ion etching to remove any conductive material from the top surface of the first dielectric layer in order to fully separate and isolate individual storage cell trenches; depositing conformally over the first conductive layer and the contact hole a second dielectric layer suitable for serving as the dielectric of the capacitor; and depositing conformally over the second dielectric layer a second conductive layer suitable for serving as the upper plate of the capacitor without providing an electrical short to the lower plate of the capacitor.
Viewed from an apparatus aspect, the present invention is directed to a memory cell for use in a dynamic random access memory. The
Dang Phuc T.
Nelms David
Paschburg Donald B.
Siemens Aktiengesellschaft
LandOfFree
Memory cell with a stacked capacitor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory cell with a stacked capacitor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory cell with a stacked capacitor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2452256