Memory cell voltage regulator with temperature correlated...

Details Memory cell voltage regulator with temperature correlated... Memory cell voltage regulator with temperature correlated...

1998-11-04

2001-02-06

Sterrett, Jeffrey (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C323S907000

Reexamination Certificate

active

06184670

ABSTRACT:

TECHNICAL FIELD
This invention relates to a temperature-related voltage generating circuit.
Specifically, the invention relates to a temperature-related voltage generating circuit having an input terminal which receives a control voltage independent of temperature, and an output terminal which delivers a temperature-related control voltage, said input and output terminals being connected together through at least an amplifier stage adapted to set an output reference voltage from a comparison of input voltages.
The invention also relates to a regulator for a drain voltage of a single-supply memory cell, which comprises a differential stage having an inverting input terminal receiving a control voltage independent of temperature and a non-inverting input terminal suitably connected to an output terminal and to a ground voltage reference, and a booster circuit connected to said output terminal and to a supply terminal of the differential stage, said supply terminal being feedback connected to the output terminal and receiving a boosted voltage from the booster circuit.
More particularly, but not exclusively, the invention relates to a temperature-related voltage generating circuit for a cell of a flash memory constructed as a memory matrix having a plurality of sectors, and the description to follow uses this field of application for illustration purpose only.
BACKGROUND OF THE INVENTION
As is well known, electrically programmable non-volatile memories are constructed as matrices of cells, each comprising a floating gate MOS transistor having respective drain and source regions.
The floating gate is realized over the semiconductor substrate and isolated therefrom by a thin layer of gate oxide. A control gate is coupled capacitively to the floating gate through a dielectric layer. Metal electrodes are provided for contacting the drain, source and control gate in order to apply predetermined voltage values to the memory cell.
By suitably biasing the cell terminals, the amount of charge present in the floating gate can be varied. The operation whereby a charge is built up in the floating gate is called “programming”, and consists of biasing the drain terminal and control gate to a predetermined value, higher than the potential of the source terminal.
A non-volatile memory circuit integrated in a semiconductor usually comprises a very large number of memory cells organized into rows (word lines) and columns (bit lines). Cells belonging to the same row share the line which drives their respective control gates. Cells belonging to the same bit line have the drain electrode in common. For programming a given cell, the word line and bit line which identify it must be applied suitable positive voltage values.
A memory cell programming is heavily affected by the voltage Vd applied to the drain terminal, that is, by the voltage present on the bit line to which that cell belongs.
In particular, for non-volatile memory cells of the FLASH type, a low value of said drain voltage Vd results in insufficient and slow programming of the cell, whereas an excessively high value results in the cell being partially erased (the so-called soft-erasing phenomenon). Thus, the optimum range for Vd is rather narrow, typically from 5 V to 6 V approximately.
The above considerations lead one to conclude that the memory circuit should be provided with a sophisticated and precise voltage regulator capable of supplying the appropriate voltage to the bit line during the programming phase.
A first prior approach to meeting this requirement is the so-called correlation by decoding, schematically illustrated in
FIG. 1
for a non-volatile memory cell M
1
.
In particular, the memory cell M
1
is connected between a ground voltage reference GND and a program voltage reference Vpp through a series of a voltage regulator
1
, connected to the program voltage reference Vpp and to a program load
2
, itself connected to the drain terminal D
1
of the memory cell M
1
via a column decoder
3
.
The regulator
1
is effective to limit the current being flowed through the memory cell M
1
during the programming phase, by smoothing a secondary program voltage Vpd, specifically the voltage present on a data bus BD between the program load
2
and the column decoder
3
.
The program load
2
conventionally comprises a logic inverter IL
1
and a transistor M
2
, specifically a PMOS type.
The drain voltage Vd of the memory cell M
1
is therefore the difference between the secondary program voltage Vpd and a voltage &Dgr;V
C
equal to the drop across the chain of decode transistors Y
0
, YN, YM of the decoder
3
and the serial resistances rd of the bit line and rs of the source terminal:
Vd=Vpd−&Dgr;V
C
  (1)
In order to limit this voltage drop &Dgr;V
C
, the value of a voltage Vpcy to be applied to the gate terminals of the chain of decode transistors Y
0
, YN, YM of the decoder
3
should be raised such that they will keep within the so-called “triode” operating range.
For flash memory cells with a dual supply, an active adjustment of the voltage drop &Dgr;V
C
can be provided using a feedback differential regulator
4
, as shown schematically in FIG.
2
.
The differential regulator
4
is connected to the drain terminal D
1
of the memory cell M
1
through the column decoder
3
, and comprises a differential stage
5
, itself connected to a redundancy decoder
6
, which is connected to the ground voltage reference GND and adapted to mirror a current I
C
flowing through the memory cell M
1
during the programming phase, via the column decoder
3
. This redundancy decoder
6
introduces a voltage drop equal to &Dgr;V
D
.
The differential stage
5
has an inverting input terminal
7
, a non-inverting input terminal
8
, and an output terminal
9
. A power supply terminal
10
of the differential stage
5
is further connected to the program voltage reference Vpp.
The inverting input terminal
7
of the differential stage
5
is connected to the ground potential reference GND through a bias transistor M
3
, spec ifically an NMOS type, which receives a control voltage V
BG
independent of temperature on its gate terminal, and through the column decoder
3
.
The bias transistor M
3
keeps the secondary program voltage Vpd stable outside the memory cell decoding phase, that is outside the current take-up phase of the cells.
The non-inverting input terminal
8
receiving a reference voltage Vref is connected, through a resistive divider R1/R2, to the redundancy decoder
6
and to the bias voltage reference Vpp.
The output terminal
9
is feedback connected to the non-inverting input terminal
8
through a current mirror configuration. In particular, the output terminal
9
is connected to the gate terminal of an output transistor M
4
, specifically an NMOS type, having its source terminal connected to the drain terminal of the bias transistor M
3
and its drain terminal connected to the drain terminal of a first mirror transistor M
5
, specifically a PMOS type, in diode configuration, that is having its drain terminal connected to the gate terminal, and its source terminal connected to the program voltage reference Vpp.
Furthermore, the gate terminal of the first mirror transistor M
5
is connected to the gate terminal of a second mirror transistor M
6
, specifically a PMOS type, having its source terminal connected to the program voltage reference Vpp and its drain terminal connected to the redundancy decoder
6
and connected to the ground voltage reference GND through an adjust transistor M
7
, specifically an NMOS type.
The adjust transistor M
7
has its source terminal connected to the ground voltage reference GND and its gate terminal connected to the control voltage V
BG
independent of temperature. In particular, this adjust transistor M
7
eliminates the mirror current contribution K*I
B
from the bias transistor M
3
, which takes up a current I
B
.
Finally, it should be noted that the output transistor M
4
and bias transistor M
3
, shown separately for convenience of illustration, are actually parts o

Affiliated with

Also associated with

Rating

Memory cell voltage regulator with temperature correlated... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory cell voltage regulator with temperature correlated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory cell voltage regulator with temperature correlated... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2569464