Active solid-state devices (e.g. – transistors – solid-state diode – Thin active physical layer which is – Tunneling through region of reduced conductivity
Reexamination Certificate
2011-07-12
2011-07-12
Coleman, W. David (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Thin active physical layer which is
Tunneling through region of reduced conductivity
C257SE27104, C257SE21663, C438S003000, C365S148000
Reexamination Certificate
active
07977667
ABSTRACT:
Methods of forming planar carbon nanotube (“CNT”) resistivity-switching materials for use in memory cells are provided, that include depositing first dielectric material, patterning the first dielectric material, etching the first dielectric material to form a feature within the first dielectric material, depositing CNT resistivity-switching material over the first dielectric material to fill the feature at least partially with the CNT resistivity-switching material, depositing second dielectric material over the CNT resistivity-switching material, and planarizing the second dielectric material and the CNT resistivity-switching material so as to expose at least a portion of the CNT resistivity-switching material within the feature. Other aspects are also provided.
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Communication pursuant to Article 94(3) EPC in counterpart European Patent Application 09743209.0 dated Mar. 3, 2011.
Clark Mark H.
Schricker April D.
Coleman W. David
Dugan & Dugan PC
SanDisk 3D LLC
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