Memory cell structure utilizing conductive buried regions

Details Memory cell structure utilizing conductive buried regions Memory cell structure utilizing conductive buried regions

1978-07-03

1980-04-15

Edlow, Martin H.

357 49, 357 51, 357 22, H01L 2704

Patent

active

041986490

ABSTRACT:
In an oxide isolated semiconductor structure having an epitaxial layer formed on a monocrystalline substrate, a buried, laterally extending PN isolation junction in said structure, and oxidized isolation regions extending through said epitaxial layer to said PN isolation junction, thereby to form a plurality of electrically isolated pockets of semiconductor material, a dopant is located in those regions of the semiconductor material directly adjacent the oxidized isolation regions to prevent unwanted current flow called "channeling." The region formed by this dopant is often referred to as the field predeposition region. Typically, to form the field predeposition region, a selected dopant is placed in the exposed surface regions of the epitaxial semiconductor material just prior to the formation of the oxidized isolation regions. The field predeposition and oxidation of the epitaxial semiconductor material also cause the formation of a conductive buried region from that portion of the field predeposition dopant in the epitaxial pockets directly adjacent the oxidized semiconductor material. If desired, a collector sink then may be formed in the epitaxial pocket without disrupting the function of the conductive buried region. The conductive buried region may be utilized to facilitate manufacture of smaller memory circuits than heretofore available, compact junction field effect transistors, and other integrated circuit structures.

REFERENCES:
patent: 3386865 (1968-06-01), Doo
patent: 3873383 (1975-03-01), Kooi
patent: 4005453 (1977-01-01), Le Can
patent: 4111724 (1978-09-01), Qgiue

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