Memory cell structure and fabrication

Details Memory cell structure and fabrication Memory cell structure and fabrication

1998-03-04

2000-07-25

Monin, Jr., Donald L.

Semiconductor device manufacturing: process

Making passive device

Trench capacitor

438387, 438389, 438391, H01L 2120

Patent

active

060936142

ABSTRACT:
A pair of memory cells for use in a DRAM are formed in a monocrystalline bulk portion of a silicon wafer by first forming a pair of vertical trenches spaced apart by a bulk portion of the wafer. After a dielectric layer is formed over the walls of each trench, the trenches are each filled with polycrystalline silicon. By a pair of recess forming and recess filling steps there is formed at the top of each trench a silicon region that was grown epitaxially with the intermediate bulk portion. Each epitaxial region is made to serve as the body of a separate transistor having its drain in the lower polysilicon fill of a trench, and its source in the monocrystalline bulk intermediate between the two epitaxial regions. The lower polysilicon fill of each trench is also made to serve as the storage node of the capacitor of each cell, with the bulk serving as the other plate of the capacitor.

REFERENCES:
patent: 5365097 (1994-11-01), Kenney
patent: 5525531 (1996-06-01), Bronner et al.
patent: 5844266 (1998-12-01), Stengl et al.

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