Memory cell structure

Details Memory cell structure Memory cell structure

2001-10-31

2003-04-15

Nelms, David (Department: 2818)

Static information storage and retrieval

Read only systems

Semiconductive

C365S051000

Reexamination Certificate

active

06549447

ABSTRACT:

BACKGROUND OF THE INVENTION
As computer and other electrical equipment prices continue to drop in price, the manufacturers of storage devices, such as memory and hard drives, are forced to lower the cost of their components. At the same time, the computer, game, television and other electrical device markets are requiring larger amounts of memory to store images, pictures, movies, music, and other data intensive files. Thus, besides reducing cost, manufactures of storage devices must also increase the storage density of their devices. This trend of increasing memory storage while at the same time reducing the cost required to create the storage has been continuous for over 20 years and will continue into the future. However, most conventional memory technologies such as magnetic disk storage, dynamic random-access memory, and even optical storage such as CD-ROMs, CD-R, CD-R/W and DVD variants are being challenged by physical limitations and high slot costs. To further increase storage density while also decreasing the cost of fabrication, a need exists to create new memory cell structures that can overcome the physical limitations imposed with conventional technology.
SUMMARY OF THE INVENTION
A memory cell has a first and second conductor. The first conductor is oriented in a first direction and the second conductor is oriented in a second direction that is substantially orthogonal to the first conductor. The first conductor has at least one edge. A state-change layer is disposed over the first conductor. A control element is partially offset over at least one edge of the second conductor. The control element is disposed between the first and second conductors. Preferably the state-change layer is a direct-tunneling junction, Lecomber tunneling junction, dielectric rupture anti-fuse switch, or phase-change switch. A memory array can be formed from a plurality of the memory cells. Optionally, creating multiple layers of the memory cells can form a three-dimensional memory array.


REFERENCES:
patent: 4792841 (1988-12-01), Nagasawa et al.
patent: 5311465 (1994-05-01), Mori et al.
patent: 5625220 (1997-04-01), Liu et al.
patent: 5734605 (1998-03-01), Zhu et al.
patent: 5835396 (1998-11-01), Zhang
patent: 5926414 (1999-07-01), Shin
patent: 5978257 (1999-11-01), Zhu et al.
patent: 6002607 (1999-12-01), Dvir
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6097625 (2000-08-01), Scheuerlein
patent: 6185121 (2001-02-01), O'Neill
patent: 6185122 (2001-02-01), Johnson et al.
patent: 6236590 (2001-05-01), Bhattacharyya et al.
patent: 6404674 (2002-06-01), Anthony et al.

Affiliated with

Also associated with

Rating

Memory cell structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory cell structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory cell structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3015665