Memory cell power scavenging apparatus and method

Details Memory cell power scavenging apparatus and method Memory cell power scavenging apparatus and method

1984-11-09

1986-12-02

Fears, Terrell W.

Static information storage and retrieval

Powering

365227, G11C 1300

Patent

active

046270345

ABSTRACT:
The present invention utilizes the power available for application to a static RAM cell in a manner which provides efficient use of the power so that greater standby power may be applied to the static RAM to increase the memory speed. The current required to maintain the memory cell in a preset state flows from the U.sub.cc source through a row of parallel memory cells and through a common bias supply and various peripheral circuits, such as decoders. A shunt voltage regulator controls the dependence of the common bias supply voltage on current fluctuations caused by addressing and deaddressing the memory cells. The invention includes an isolation device for isolating a particular row of memory cells when it is addressed without disturbing the bias on other memory cell rows. Similarly, the reference voltages of each of the peripheral circuits can be made independent of the common bias supply voltage and independent of the other peripheral circuits by the use of a local voltage regulator on each peripheral.

REFERENCES:
patent: 4422162 (1983-12-01), Davis et al.

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