Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2002-08-26
2004-04-27
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C257S317000
Reexamination Certificate
active
06728135
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior French Patent Application No. 0111381, filed Sep. 3, 2001, the disclosure of which is hereby incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuits, and more particularly to memory cells or memory locations of the FAMOS-type (Floating-Gate Avalanche-Injection MOS), that is to say those based on a FAMOS-type transistor.
2. Description of Related Art
It will be recalled that the FAMOS (Floating-Gate Avalanche-Injection MOS) technology uses the memory location obtained with a p-type MOS transistor, the single gate of which is isolated and not electrically connected. This single gate is therefore floating.
This memory location may be obtained without adding further steps to the basic technological process for the fabrication of a p-type MOS transistor. Unlike the other memory locations, for example of the FLASH, EPROM or EEPROM type, which comprise a floating gate and a control gate, the FAMOS memory cell comprises only a single floating gate.
To erase a FAMOS memory location, ultraviolet radiation may be employed. This type of memory location is more particularly used as an OTP (one-time programmable) memory.
At the present time, the configuration of a FAMOS memory cell relies on a linear transistor, such as one having a rectangular gate overlapping an active region and thus defining the two, source and drain, electrodes of the transistor. The memory location is therefore perfectly symmetrical and its electrical characteristics in programming mode and in read mode are independent of the way in which the transistor is connected up.
The only possibility of then having several programming levels, and therefore several read levels, for example four programming levels, i.e., 2 bits/memory cell, is for the programming time to be finely controlled, thereby allowing more or fewer charges to be injected into the floating gate.
However, such a method is extremely difficult to implement and requires a critical control mechanism so as to guarantee a temporal programming window compatible with the performance of the read circuit. Accordingly, a need exists to overcome this difficulty and to provide a memory cell of FAMOS type having several programming logic levels.
SUMMARY OF THE INVENTION
The present invention provides a FAMOS memory location capable of having at least three if not more, completely natural programming levels, that is, levels which are solely dependent on the physical characteristics of the memory location and on the various bias voltages applied, but being independent of the length of time these bias voltages are applied beyond a certain saturation time, typically of the order of 1 ms. In fact, according to the present invention, the memory location will naturally reach, by itself, beyond this saturation time, an equilibrium corresponding to a programming level depending merely on the bias voltages applied.
The invention therefore provides a memory device, comprising a FAMOS memory location having a single floating gate overlapping an active surface of a semiconductor substrate according to at least two asymmetrical overlap profiles so as to define at least two electrodes in the active region. Moreover, the device includes memory location programming means capable of selectively applying different predetermined sets of bias voltages to the electrodes so as to confer at least three programming logic levels on the memory location.
The FAMOS memory location according to the present invention has an asymmetrical configuration. It therefore provides for several separate programming levels to be created “naturally”, according to the bias voltages applied to the various electrodes. After a certain time, the memory location reaches its equilibrium by itself as regards the number of charges injected into the gate, thereby making it possible to define a programming logic level.
Moreover, such a FAMOS cell according to the present invention requires no modification to the conventional CMOS fabrication process, especially with regard to the implantations. It is only the geometry of the gate, in combination with different sets of bias voltages, which allows the various programming levels to be obtained. In other words, the memory location according to the invention is directly compatible with a CMOS logic process, which by nature is not designed for the production of non-volatile memory cells.
According to one embodiment of the invention, the floating gate overlaps the active surface according to two asymmetrical overlap profiles so as to define two electrodes. This is especially the case when the gate has an annular configuration.
One of the three programming logic levels corresponds, for example, to an erased memory location, the programming means then applying no bias voltage to the electrodes of the memory location.
Moreover, to confer a second programming logic level on the memory location, the programming means define, for example, a first electrode as being the drain of the memory location transistor and the second electrode as being the source of the transistor and apply corresponding first predetermined source and drain bias voltages.
To confer a third programming logic level on the memory location, the programming means define, for example, the first electrode as being the source of the memory location transistor and the second electrode as being the drain of the transistor, and apply corresponding second predetermined bias voltages.
In practice, the programming means may, for example, apply in the first case a voltage of 0 volts to the first electrode and 5 volts to the second electrode and apply in the second case a voltage of 5 volts to the first electrode and 0 volts to the second electrode.
When the gate has an annular configuration, the first electrode may be defined as being the central electrode located inside the gate, while the second electrode may be defined as being the peripheral electrode located outside the gate.
According to another embodiment of the invention, the floating gate has a figure-eight configuration defining a peripheral electrode located outside the gate, a first central electrode located inside the first loop of the eight and a second central electrode located inside the second loop of the eight. The memory location programming means are then capable of selectively applying different sets of predetermined bias voltages to the electrodes so as to confer more than three, for example four or even more, programming logic levels on the memory location.
In this regard, the programming means may define one of the three electrodes as being the drain of the memory location transistor, another of the three electrodes as being the source of the transistor and the third electrode as being a control electrode. The programming means are therefore capable, for example, of applying corresponding bias voltages to the source and to the drain and of selectively applying different voltages, lying between the source voltage and the drain voltage, to the control electrode so as to obtain different programming logic levels, respectively.
Of course, it is also possible to invert the source and the drain in order to obtain even more programming logic levels.
It is also possible for one of the programming logic levels to correspond to an erased memory location, the programming means then applying no bias voltage to the electrodes of the memory location.
As an example, the peripheral electrode may correspond to the source of the transistor and the drain may correspond to one of the two central electrodes.
The device according to the invention also advantageously includes means for reading the programming logic levels, which means are capable of applying specific bias voltages to the source and to the drain of the memory location transistor so as to allow the drain current to be measured.
Advantageously, a higher drain current may be obtained when the source is considere
Caspar Daniel
Dray Cyrille
Fournel Richard
Fleit Kain Gibbons Gutman Bongini & Bianco P.L.
Gibbons Jon A.
Jorgenson Lisa K.
Nguyen Tan T.
STMicroelectronics S.A.
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