Memory cell of nonvolatile semiconductor memory device

Details Memory cell of nonvolatile semiconductor memory device Memory cell of nonvolatile semiconductor memory device

2002-01-23

2003-04-08

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S230060, C365S185170, C365S185110

Reexamination Certificate

active

06545913

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device having floating gate type MOSFETs as memory cells.
2. Description of the Related Art
Conventionally, EEPROM and UVEPROM are known as the nonvolatile semiconductor memory device with a floating gate structure, for example. In the EEPROM, data is electrically written in or programmed and electrically erased. With a memory cell in the EEPROM, data can be programmed by injecting or emitting electrons into or from the floating gate via an oxide film with a thickness of approx. 100 Å which is extremely thinner than a gate oxide film by use of the tunnel effect. The EEPROM is explained in detail in U.S. Pat. No. 4,203,158 (Frohman-Bentchkowsky et al. “ELECTRICALLY PROGRAMMABLE AND ERASABLE MOS FLOATING GATE MEMORY DEVICE EMPLOYING TUNNELING AND METHOD OF FABRICATING SAME”).
However, since, in the above EEPROM, two transistors are,used to constitute a single memory cell, the memory cell size becomes large and the chip cost will increase.
For the above reason, ultraviolet erasable non-volatile semiconductor memory devices or UVEPROM has an advantage in attaining high integration density, in which each memory cell is formed of a single transistor.
In the UVEPROM, data can be electrically programmed and erased by applying ultraviolet rays thereto. As described above, in the UVEPROM, each memory cell is formed of a single transistor so that the chip size can be reduced for the same memory scale or capacity as that of the EEPROM.
However, in the UVEPROM, a high power source voltage is required to program data. That is, in order to inject electrons into the floating gate of a selected memory cell, a high voltage is applied between the control gate and drain to cause impact ionization in an area near the drain region, injecting the electrons thus generated into the floating gate. For this purpose, it becomes necessary to provide a power source of high voltage for data programming outside the memory device. In contrast, since electrons are injected into or emitted from the floating gate by the tunnel effect in the EEPROH, it is not necessary to use such a programming power source as is used in the UVEPROM and data can be programmed by an output voltage of a booster circuit provided in the same chip as that of the memory device. Therefore, the EEPROM can be operated on a single power source voltage of 5 V.
As described above, the UVEPROM can be formed at a higher integration density in comparison with the EEPROM. However, in general, since a single contact portion is formed for each common drain of two memory cell transistors, the number of contact portions increases. Increase in the number of contact portions is an obstruction to the attainment of high integration and large memory capacity. For this reason, the UVEPROM can be formed at a higher integration density than the EEPROM, but can be further improved in its integration density.
SUMMARY OF THE INVENTION
One aspect of the present invention provides a row line selection circuit. The row line selection circuit comprises a first decoding section which receives a first address signal and generates a plurality of first selection signals in response to the first address signal; a second decoding section which receives a second address signal and generates a plurality of second selection signals in response to the second address signal; and a plurality of N-channel type MOS transistors each of which has a gate, one end of a current path of each of the plurality of N-channel type MOS transistors being connected in such a manner as to receive one of the plurality of second selection signals, and each of the plurality of N-channel type MOS transistors transferring one of the plurality of second selection signals to a row line for selecting the row line in response to one of the plurality of first selection signals, wherein the plurality of N-channel type transistors are classified into groups, each group including a predetermined number of the N-channel type transistors which are prepared in correspondence with row lines lying adjacent to each other; one of the plurality of first selection signals is supplied to the gate of the predetermined number of N-channel type MOS transistors in one of the groups; one of the plurality of second selection signals is supplied to a corresponding one of the predetermined number of N-channel type MOS transistors in each group; and the row line is selected in response to one of the plurality of first selection signals generated in the first decoding section and one of the plurality of second selection signals generated in the second decoding section.
Another aspect of the present invention provides a row line selection circuit. The row line selection circuit comprises a first decoding section which receives a first address signal and generates a plurality of first selection signals in response to the first address signal; a second decoding section which receives a second address signal and generates a plurality of second selection signals in response to the second address signal; and a plurality of switching means for transferring one of the plurality second selection signals to a row line in response to one of the plurality of first selection signals in order to select the row line, wherein the plurality of switching means are classified into groups, each group including a predetermined number of the switching means which are prepared in correspondence with row lines lying adjacent to each other; one of the plurality of first selection signals is supplied to the predetermined number of switching means in one of the groups; one of the plurality of second selection signals is supplied to a corresponding one of the predetermined number of switching means in each group; and the plurality of second selection signals do not affect the row lines when the plurality of switching means are turned off; and the row line is selected in response to one of the plurality of first selection signals generated in the first decoding section and one of the plurality of second selection signals generated in the second decoding section.
Still another aspect of the present invention provides a row line selection circuit. The row line selection circuit comprises a first decoding section which receives a first address signal and generates a plurality of first selection signals in response to the first address signal; a second decoding section which receives a second address signal and generates a plurality of second selection signals in response to the second address signal; and a plurality of transfer circuits for selecting a row line, each of the plurality of circuits transfer one of the plurality of second selection signals to the row line and a low level component of one of the plurality of second selection signals while maintaining a voltage level of the low level component in response to one of the plurality of first selection signals, the plurality of transfer circuits are classified into groups, each group including a predetermined number of the transfer circuits which are prepared in correspondence with row lines lying adjacent to each other; one of the plurality of first selection signals is supplied to the predetermined number of transfer circuits in one of the groups; one of the plurality of second selection signals is supplied to a corresponding one of the predetermined number of transfer circuits in each group; and the row line is selected in response to one of the plurality of first selection signals generated in the first decoding section and one of the plurality of second selection signals generated in the second decoding section.


REFERENCES:
patent: 4099196 (1978-07-01), Simko
patent: 4203158 (1980-05-01), Frohman-Bentchkowsky et al.
patent: 4233526 (1980-11-01), Kurogi et al.
patent: 4344005 (1982-08-01), Stewart
patent: 4377857 (1983-03-01), Tickle
patent: 4425632 (1984-01-01), Iwahashi et al.
patent: 4447895 (1984-05-01), Asano
patent: 4467453 (1984-08-01), Chiu et al.
patent: 4500975 (19

Affiliated with

Also associated with

Rating

Memory cell of nonvolatile semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory cell of nonvolatile semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory cell of nonvolatile semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3087827