Memory cell of nonvolatile semiconductor memory device

Details Memory cell of nonvolatile semiconductor memory device Memory cell of nonvolatile semiconductor memory device

1999-02-26

2001-07-31

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Floating gate

Particular connection

C365S185120, C365S185170

Reexamination Certificate

active

06269021

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device having floating gate type MOSFETs as memory cells.
2. Description of the Related Art
Conventionally, EEPROM and UVEPROM are known as the nonvolatile semiconductor memory device with a floating gate structure, for example. In the EEPROM, data is electrically written in or programmed and electrically erased. With a memory cell in the EEPROM, data can be programmed by injecting or emitting electrons into or from the floating gate via an oxide film with a thickness of approx. 100 Å which is extremely thinner than a gate oxide film by use of the tunnel effect. The EEPROM is explained in detail in U.S. Pat. No. 4,203,158 (Frohman-Bentchkowsky et al. “ELECTRICALLY PROGRAMMABLE AND ERASABLE MOS FLOATING GATE MEMORY DEVICE EMPLOYING TUNNELING AND METHOD OF FABRICATING SAME”).
However, since, in the above EEPROM, two transistors are,used to constitute a single memory cell, the memory cell size becomes large and the chip cost will increase.
For the above reason, ultraviolet erasable non-volatile semiconductor memory devices or UVEPROM has an advantage in attaining high integration density, in which each memory cell is formed of a single transistor. In the UVEPROM, data can be electrically programmed and erased by applying ultraviolet rays thereto. As described above, in the UVEPROM, each memory cell is formed of a single transistor so that the chip size can be reduced for the same memory scale or capacity as that of the EEPROM.
However, in the UVEPROM, a high power source voltage is required to program data. That is, in order to inject electrons into the floating gate of a selected memory cell, a high voltage is applied between the control gate and drain to cause impact ionization in an area near the drain region, injecting the electrons thus generated into the floating gate. For this purpose, it becomes necessary to provide a power source of high voltage for data programming outside the memory device. In contrast, since electrons are injected into or emitted from the floating gate by the tunnel effect in the EEPROM, it is not necessary to use such a programming power source as is used in the UVEPROM and data can be programmed by an output voltage of a booster circuit provided in the same chip as that of the memory device. Therefore, the EEPROM can be operated on a single power source voltage of 5 V.
As described above, the UVEPROM can be formed at a higher integration density in comparison with the EEPROM. However, in general, since a single contact portion is formed for each common drain of two memory cell transistors, the number of contact portions increases. Increase in the number of contact portions is an obstruction to the attainment of high integration and large memory capacity. For this reason, the UVEPROM can be formed at a higher integration density than the EEPROM, but can be further improved in its integration density.
SUMMARY OF THE INVENTION
An object of this invention is to provide an EEPROM in which data can be electrically programmed, the memory cell size can be reduced and the cost can be lowered.
Another object of this invention is to provide a UVEPROM in which the number of contact portions can be reduced to further reduce the chip size and the high integration density and low cost can be attained.
According to one embodiment of this invention, there is provided a nonvolatile semiconductor memory device which comprises a selection transistor which is connected at one end to a column line and whose gate is connected to a row line; and a plurality of cell transistors which are connected in series between the other end of the selection transistor and a reference potential and whose control gates are connected to row lines, wherein electrons are emitted from a floating gate to a drain of the cell transistor or holes are injected from the drain to the floating gate in the data programming mode.
In a first embodiment of this invention, there is provided an EEPROM in which the selection transistor can be commonly used for the cell transistors so that the memory cell can be formed of substantially one cell transistor. Therefore, the size of the memory cell can be reduced, and the high integration density and low cost can be attained.
In a second embodiment of this invention, there is provided a UVEPROM in which a single contact portion can be commonly used for three or more cell transistors, thereby reducing the number of contact portions. Thus, the high integration density and low cost can be attained.


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