Memory cell layout structure for a semiconductor memory device

Details Memory cell layout structure for a semiconductor memory device Memory cell layout structure for a semiconductor memory device

1995-06-05

1996-10-15

Yoo, Do Hyun

Static information storage and retrieval

Format or disposition of elements

365 63, 365149, G11C 502, G11C 506

Patent

active

055661041

ABSTRACT:
A plurality of memory cells are arranged spaced by an equal distance along one direction on a main surface of a semiconductor substrate, thus forming a first memory cell group, and a second memory cell group is arranged adjacent to the first memory cell group. In the second memory cell group, a plurality of memory cells are arranged spaced by the same distance as the first memory cell group, with central position of each memory cell of the second memory cell group being shifted by 1/6 with respect to the central position of each memory cell of the first memory cell group. Bit line pair and word lines are provided in a single layer, detouring storage node contacts.

REFERENCES:
patent: 5365474 (1994-11-01), Motonami
patent: 5383151 (1995-11-01), Omishi et al.
patent: 5396451 (1995-03-01), Ema
patent: 5416734 (1995-05-01), Hidaka et al.
"A Study of Close Packed Folded Bit-Line Cell Array (CPF) and Three Phase Folded Bit-Line Array/Circuit (TPF) for DRAM's", T. Saeki et al, pp. 5-256, Mar. 15, 1991.

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