Memory cell integrated structure with corresponding biasing devi

Details Memory cell integrated structure with corresponding biasing devi Memory cell integrated structure with corresponding biasing devi

1999-04-21

2000-11-21

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518527, G11C 1134

Patent

active

061512516

ABSTRACT:
A biasing device for biasing a memory cell having a substrate bias terminal associated therewith. The biasing device includes a first sub-threshold circuitry block adapted to supply an appropriate current during the device standby phase through a restore transistor connected between a supply voltage reference and the substrate bias terminal of the memory cell, and having a control terminal connected to a bias circuit, in turn connected between the supply voltage reference and a ground voltage reference to drive the restore transistor with a current of limited value. The device further includes a second feedback block for fast charging the substrate bias terminal, being connected between the supply voltage reference and the ground voltage reference and comprising a first bias transistor having a control terminal connected to the ground voltage reference via a stabilization transistor, having in turn a control terminal connected to an output node, and to the control terminal of a first regulation transistor connected between the supply voltage reference and the ground voltage reference, the stabilization transistor and first regulation transistor providing feedback for the bias transistor, thereby to restrict the voltage range of the output node.

REFERENCES:
patent: 5243559 (1993-09-01), Murai
patent: 5461338 (1995-10-01), Hirayama et al.
patent: 5548146 (1996-08-01), Kuroda et al.
patent: 5576995 (1996-11-01), Sato et al.

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