Memory cell having programmed margin verification

Details Memory cell having programmed margin verification Memory cell having programmed margin verification

1997-10-20

1998-08-18

Le, Vu A.

Static information storage and retrieval

Floating gate

Particular biasing

365188, 36518907, 365201, G11C 1134

Patent

active

057966559

ABSTRACT:
A memory cell having programming voltage margin verification is provided. The memory cell includes a voltage comparator having a differential input with first and second inputs and bias circuitry for generating a differential input voltage. A voltage offset is applied to the second input of the comparator to provide an input offset voltage. A programming voltage is received for programming the memory cell and the memory cell provides an output signal. To verify an unprogrammed state voltage margin of the memory cell, a margin detection circuitry receives a verification check signal and the output is monitored to determine whether the unprogrammed state voltage margin is proper. To verify a proper programmed state voltage margin of the memory cell, current is sensed through the programming input and a determination of a proper programmed state voltage margin is determined as a function of the sensed current.

REFERENCES:
patent: 5014098 (1991-05-01), Schlais et al.
patent: 5572472 (1996-11-01), Kearney et al.
patent: 5592416 (1997-01-01), Bonitz et al.

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