Memory cell having means for maintaining the gate and substrate

Details Memory cell having means for maintaining the gate and substrate Memory cell having means for maintaining the gate and substrate

1989-03-23

1991-09-24

Tupper, Robert S.

Static information storage and retrieval

Floating gate

Particular biasing

365154, 365182, 365228, G11C 1100, G11C 1140

Patent

active

050519565

ABSTRACT:
A memory cell is provided comprising a bistable latch (I1, I2) having first and second nodes (NODE 1, NODE 2) and a nonvolatile transistor (NV1). The control gate of the nonvolatile transistor is connected to the first node and either the source or drain is connected to the second node. A switching transistor is provided for maintaining the control gate and the substrate of the nonvolatile transistor at substantially the same potential during volatile operation of the latch, thereby reducing voltage stress which would lead to charge tunnelling to or from the floating gate. In this way, disturbance of the floating gate charge is avoided during volatile operation. The cell is particularly suited to silicon gate fabrication technology.

REFERENCES:
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patent: 4313106 (1982-01-01), Hsu
patent: 4333166 (1982-06-01), Edwards
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patent: 4348745 (1982-09-01), Schmitz
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Lee, Douglas J., et al; "Control Logic and Cell Design for a 4K NVRAM;" IEEE Journal of Solid-State Circuits; vol. SC-18, No. 5, Oct. 1983; pp. 525-531.

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