Static information storage and retrieval – Floating gate – Particular biasing
Patent
1999-04-28
2000-10-10
Nelms, David
Static information storage and retrieval
Floating gate
Particular biasing
365 63, 36518528, 36518529, G11C 1604
Patent
active
061308404
ABSTRACT:
A memory cell has an erasable Frohmann-Bentchkowsky p-channel memory transistor and an n-channel MOS access transistor. Eraseability is provided by utilizing a p-well which is formed adjacent to the memory transistor, and a floating gate which is formed over both the channel of the memory transistor and the p-well.
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D. Frohmann-Bentchkowsky, "A Fully Decoded 2048-bit Electrically-Programmable MOS-ROM," 1971 IEEE International Solid-State Circuits Conference, Feb. 18, 1971, ISSCC Digest of Technical papers, pp. 80-81; p. 200, Univ. of Pennsylvania.
Bergemont Albert
Kalnitsky Alexander
Auduong Gene N.
National Semiconductor Corporation
Nelms David
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