Memory cell having a plural transistor transmission gate and met

Static information storage and retrieval – Floating gate – Particular biasing

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Details

365149, 365156, 365145, 257316, 257326, G11C 1604, G11C 1122, G11C 1124

Patent

active

058986197

ABSTRACT:
A memory circuit and method of formation uses a transmission gate (24) as a select gate. The transmission gate (24) contains a transistor (30) which is an N-channel transistor and a transistor (28) which is a P-channel transistor. The transistors (28 and 30) are electrically connected in parallel. The use of the transmission gate (24) as a select gate allows reads and writes to occur to a memory cell storage device (i.e. a capacitor (32), a floating gate (22), etc.) without a significant voltage drop occurring across the transmission gate. In addition, EEPROM technology is more compatible with EPROM/flash technology when using a transmission gate as a select gate within EEPROM devices.

REFERENCES:
patent: 3521242 (1970-07-01), Katz
patent: 4441169 (1984-04-01), Sasaki
patent: 4633438 (1986-12-01), Kume
patent: 4779231 (1988-10-01), Holzapfel
patent: 4910709 (1990-03-01), Dhong
patent: 4912749 (1990-03-01), Maruyama
patent: 4995002 (1991-02-01), Yamada
patent: 5040147 (1991-08-01), Yoshizawa
patent: 5146429 (1992-09-01), Kawai
"Stress Induced Leakage Current Limiting to Scale Down EEPROM Tunnel Oxide Thickness", by Naruke et al., 1988 IEDM, pp. 424-427.

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