Memory cell for SRAM with a dielectric layer over a gate electro

Details Memory cell for SRAM with a dielectric layer over a gate electro Memory cell for SRAM with a dielectric layer over a gate electro

1985-11-15

1989-01-10

Edlow, Martin H.

Electrical resistors

Incased, embedded, or housed

Element in insulation with outer metallic sheath

357 51, 357 41, 357 235, 338334, 361311, H01L 2934, H01L 2702, H01L 2978, H01L 2904

Patent

active

047977256

ABSTRACT:
A static memory cell including a pair of field-effect transistors, characterized by the provision of highly dielectric layers in combination with the field-effect transistors, wherein each of the highly dielectric layers is located directly on a polysilicon gate electrode layer formed on a silicon dioxide insulating layer bridging the channel region of each of the field-effect transistors. The gate electrode layer of one field-effect transistor is held in direct contact with the drain region of the other field-effect transistor and the two highly dielectric layers are covered with a polysilicon conductive layer electrically connected to a supply voltage source so that each field-effect transistor has its drain region connected to the supply voltage source through one dielectric layer and its gate electrode layer connected to the voltage source through the other dielectric layer. The provision of the highly dielectric layers is useful for precluding the memory cell from inviting a soft error during use of the memory cell as would otherwise be caused by alpha radiation and thus guarantee stabilized performance of the memory cell.

REFERENCES:
patent: 3264531 (1966-08-01), Dickson
patent: 3781610 (1973-12-01), Bodway
patent: 4416049 (1983-11-01), McElroy
patent: 4458407 (1984-07-01), Hoeg et al.
patent: 4538244 (1985-08-01), Sugo et al.
patent: 4590508 (1986-05-01), Hirakawa et al.

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