Memory cell for a programmable logic device (PLD) avoiding pumpi

Details Memory cell for a programmable logic device (PLD) avoiding pumpi Memory cell for a programmable logic device (PLD) avoiding pumpi

1995-11-17

1997-09-09

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular connection

36518518, 36518524, G11C 1134

Patent

active

056663099

ABSTRACT:
A memory cell for a programmable logic device (PLD) and method for programming the memory cell. The memory cell includes components typically found in a memory cell for a PLD including an NMOS transistor having a floating gate, and two capacitors coupled to the floating gate, one capacitor being a tunneling capacitor enabling charge to be added to and removed from the floating gate. The memory cell further includes an NMOS pass gate transistor for supplying charge to the tunneling capacitor, but unlike conventional NMOS pass gates, it has a reduced threshold so that during programming when a programming voltage is applied to its drain, it can be turned on with an identical programming voltage applied to its gate, rather than requiring that its gate voltage be pumped above its drain voltage during programming. The reduced threshold can be obtained by removing the vt implant and punch through implant normally provided in its channel, or by other means.

REFERENCES:
patent: 4460979 (1984-07-01), Brahmbhatt
patent: 4831589 (1989-05-01), Brahmbhatt
patent: 4885719 (1989-12-01), Brahmbhatt
patent: 5272368 (1993-12-01), Turner et al.
patent: 5331590 (1994-07-01), Josephson et al.

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