Memory cell for a dense EPROM

Details Memory cell for a dense EPROM Memory cell for a dense EPROM

1986-12-10

1990-08-07

Carroll, J.

357 54, H01L 2978, H01L 2934

Patent

active

049472216

ABSTRACT:
A memory cell has a first capacitance between a floating gate and a channel region and a second capacitance between a control gate and the floating gate. The second capacitance is less than said first capacitance, preferably much less, and there is self-alignment in two directions, resulting in a compact cell. The floating gate can have a textured surface facing the control gate. The control gate can also shift the cell operation from the enhancement mode into the depletion mode.

REFERENCES:
patent: 3984822 (1976-10-01), Simko et al.
patent: 4272774 (1981-06-01), Boettcher
patent: 4295150 (1981-10-01), Adam
patent: 4332077 (1982-06-01), Sheng Teng Hsu
patent: 4519849 (1985-05-01), Korshetol
patent: 4577215 (1986-03-01), Stewart et al.
R. M. Anderson et al., "Evidence for Surface Asperity Mechanism of Conductivity in Oxide Grown on Polycrystalline Silicon", Journal of Applied Physics, vol. 43 (1977), pp. 4834-4836.

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