Memory cell device having vertical channel and double gate...

Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Combined with field effect transistor

Reexamination Certificate

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Details

C257S250000, C257S302000

Reexamination Certificate

active

07863643

ABSTRACT:
A memory cell device having a vertical channel and a double gate structure is provided. More specifically, a memory cell device having a vertical channel and a double gate structure is characterized by having a pillar active region with a predetermined height, which is including a first semiconductor layer forming a first source/drain region, a second semiconductor layer being placed under the first semiconductor layer with a predetermined distance and forming a second source/drain region, and a third semiconductor layer forming a body region and a channel region between the first semiconductor layer and the second semiconductor layer, and therefore, there is no need for unnecessary contacts when it is used as a unit cell for any type of memory array, not to speak of NOR type flash memory array. And the present invention makes to program/erase more effectively and increase the read speed and the amount of sensing current.

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patent: 10-2005-0094200 (2005-09-01), None

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