Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2001-01-16
2002-04-30
Ho, Hoai V. (Department: 2818)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S241000, C438S242000
Reexamination Certificate
active
06379978
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a memory cell configuration in which an electrical resistance of a memory element represents an information item and can be influenced by a magnetic field, and a method for fabricating it.
There are elements whose electrical resistances can be influenced by magnetic fields. These include the so-called giant magnetoresistive (GMR) elements, which have at least two ferromagnetic layers and a nonmagnetic layer disposed in between and exhibit the so-called giant magnetoresistive (GMR) effect. The GMR effect is the term used to denote the fact that an electrical resistance of the GMR element is dependent on whether the magnetizations in the two ferromagnetic layers are oriented parallel or antiparallel to one another. A magnetic field can change the magnetization direction of one or both layers and, consequently, the electrical resistance of the GMR element. In the case of a current flow perpendicular to the planes of the layers of the memory element (i.e. current perpendicular to plane (CPP) configuration), the GMR element has a different electrical resistance and magnetoresistance effect than in the case of a current flow parallel to the planes of the layers of the memory element (current in plane (CIP) configuration) (see the reference by F. W. Patten et al., title “Overview of the DARPA Non-Volatile Magnetic Memory Program”, IEEE 1996, pages 1-2).
If the nonmagnetic layer is conductive, then the term referred to is spin valve (SV) effect. If the nonmagnetic layer is insulating, then the term referred to is spin tunneling (ST) or tunneling magnetoresistance (TMR) effect (see Patten et al. loc. cit.).
In order to be able to orient the magnetization directions of the two ferromagnetic layers parallel or antiparallel to one another using a field which permeates both layers, the threshold fields, i.e. the smallest fields which are necessary for changing the magnetization directions, are different for the layers. The magnitude of the threshold fields can be influenced by the choice of materials, by the thickness of the layers, by the size and direction of the magnetic field during the deposition of the layers, and by the temperature during the deposition of the layers (see the reference by J. S. Moodera et al., J. Appl. Phys. 79 (8) 1996, pages 4724 to 4729). Another possibility for influencing the threshold field of a ferromagnetic layer is to dispose, adjoining the ferromagnetic layer, an antiferromagnetic layer which virtually fixes the magnetization direction of the ferromagnetic layer and thus effectively increases the threshold field of the ferromagnetic layer.
The reference by D. D. Tang et al., IEDM 95, pages 997 to 999, and the reference by D. D. Tang et al., IEEE Trans. on Magnetics, Vol. 31, No. 6, 1995, pages 3206 to 3208, propose using GMR elements of this type as memory elements in a memory cell configuration. The magnetization direction of a first ferromagnetic layer of a memory element is fixed by an adjacent antiferromagnetic layer. The magnetization direction of a second ferromagnetic layer can be altered by a magnetic field that is larger than the threshold field of the second layer, without altering the magnetization direction of the first layer. In order that each memory element can be programmed separately, write lines are provided, which cross in the region of the memory elements. In order to program the memory cell, the magnetic field is generated by current being sent through the associated two write lines. The current intensities are dimensioned in such a way that only the superposition of the magnetic fields of both write lines suffices to exceed the minimum intensity required to alter the magnetization direction of the second ferromagnetic layer. The memory elements are connected in series. Each row forms a bit line. The write lines are electrically insulated from the bit lines and the memory elements. In order to read the memory cell, i.e. in order to determine the magnetization direction of its second layer, first a read current is sent through the corresponding bit line and the total voltage dropped across the latter is measured. The two write lines then generate a magnetic field that is larger than the threshold field of the second layer. If the direction of the magnetic field corresponds to the original, i.e. the information-representing magnetization direction of the second layer, then the total voltage on the bit line does not change. Otherwise, the magnetic field changes the magnetization direction of the second layer with the consequence that the total voltage changes.
The reference by S. Tehrani et al., IEDM 96, page 193 et seq., proposes using, as a memory element, a GMR element which has ferromagnetic layers of different thicknesses. The magnetic field for writing in information is dimensioned in such a way that it exceeds the minimum strength for changing the magnetization direction of the thicker of the two ferromagnetic layers. For the read-out, i.e. for the determination of the magnetization direction of the thicker layer, a magnetic field is set which magnetizes the thinner but not the thicker of the two layers in a distinguished direction, and the associated voltage on a bit line is measured. Afterward, a magnetic field is set which magnetizes the thinner layer in the opposite direction and the associated voltage on the bit line is measured. The magnetization direction of the thicker layer is obtained from the sign of the difference between the voltages. The magnetization in the thicker of the two ferromagnetic layers remains uninfluenced by the read-out.
The read-out operation by comparing two successively measured voltages requires an increased outlay on circuitry and takes a long time.
U.S. Pat. No. 5,640,343 describes an MRAM cell configuration in which memory elements are disposed in an x-y grid. First lines run perpendicularly to second lines. The memory elements are each connected between one of the first lines and one of the second lines. For each memory element there are a multiplicity of parallel current paths, which make reliable determination of resistance more difficult.
U.S. Pat. No. 5,173,873 describes an MRAM cell configuration in which a memory element has a magnetoresistive layer disposed between two ferromagnetic layers. The magnetization direction of one of the ferromagnetic layers is changed by an external magnetic field. The other of the ferromagnetic layers has a higher coercive force and its magnetization direction is not altered by the magnetic field. The magnetic field is generated by a line running past the memory element. The sign of the current flow through the line determines whether the information 0 or 1 is written to the memory element. The line is connected to a write line via a transistor that selects the memory element from among other memory elements during writing. In order to write and in order to read out the information, a plurality of transistors and a plurality of lines are provided per memory element, which select the memory element from among other memory elements. This MRAM cell configuration has the disadvantage that because of the many transistors and lines per memory cell, its packing density is low.
SUMMARY OF THE INVENTION:
It is accordingly an object of the invention to provide a memory cell configuration in which an electrical resistance of a memory element represents an information item and can be influenced by a magnetic field, and a method for fabricating it that overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, in which the information item can be read out with a reduced outlay on circuitry or faster.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory cell configuration containing a memory cell having a memory element and a transistor connected in series with the memory element. The memory element has an electrical resistance representing an information item that can be influenced by a magnetic field.
Bertagnolli Emmerich
Goebel Bernd
Jacobs Hermann
Schwarzl Siegfried
Ho Hoai V.
Infineon - Technologies AG
Lerner Hernert L.
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