Memory cell configuration and production process therefor

Details Memory cell configuration and production process therefor Memory cell configuration and production process therefor

1999-09-24

2001-08-14

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making passive device

Trench capacitor

C438S243000, C438S249000, C438S392000, C257S301000, C257S303000, C257S306000, C257S310000

Reexamination Certificate

active

06274453

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to a memory cell configuration with many ferroelectric memory cells (ferroelectric memories or FeRAMs) or a nonvolatile random access memory (NVPRAM or DRAM) with dielectric memory cells and a corresponding production process. The term “semiconductor substrate” is to be understood in the general sense here, and hence refers to a wafer substrate, an epitaxial substrate, a well substrate, and so forth.
Although it can be applied to memories containing any arbitrary foundation material, the present invention and the fundamental problems involved will be explained here in terms of a silicon-based substrate.
In general, a DRAM contains a memory cell configuration whose individual memory cells have a selection transistor and a capacitor connected to it. A read-only memory (ROM) has only a single transistor as its memory cell.
The memory cell configurations are based initially on predominantly planar concepts. In view of the ever-increasing packing density, it has already been proposed for mask-ROM applications that the cell surface of the memory be convoluted by making parallel longitudinal trenches, thus reducing the projection of the cell surface onto the wafer surface by up to 50%. In DRAMs, it is known in particular to utilize the vertical direction for forming capacitors in the form of trench or stacked capacitors.
The general goal in memory technology is to produce single-transistor cells that are markedly smaller than 8F
2
, where F is the minimum feature size of the applicable technology.
Until now, most memory concepts with an area of less than 6F
2
include vertical transistors.
From Published, Non-Prosecuted German Patent Application DE 195 14 834 A, a read-only memory cell configuration is known that has memory cells with a vertical MOS transistor. The memory cells are disposed along opposite flanks of striplike, parallel isolation trenches. If a width and spacing of the isolation trenches are chosen to be large, then the minimum space required per memory cell is theoretically 2F
2
, where F is the minimum feature size of the technology.
Published, Non-Prosecuted German Patent Application DE 195 10 042 A discloses a read-only memory cell configuration in which the memory cells are disposed in a parallel row, and longitudinal trenches are provided that extend parallel to the rows. The rows are each disposed in alternation on the main face between adjacent longitudinal trenches and on the bottom of the longitudinal trenches. Vertical isolation features are provided for the mutual isolation of the memory cells, which each include one MOS transistor. Word lines extend crosswise to the rows, and they are each connected to the gate electrodes of MOS transistors disposed along different rows.
The minimum space per memory cell here is theoretically 2F
2
, where F is the minimum feature size of the technology. This makes it possible to utilize virtually the entire silicon surface area as an active face. Thus very small cell surfaces can be achieved without having to have recourse to vertical transistors. The result is that process costs are lowered, and reliability is increased. Especially in ferroelectric memory cells, in which the leakage current requirements are not quite as stringent as in the DRAM, such planar concepts have great potential.
From Published, Non-Prosecuted German Patent Application DE 195 43 539 A, a RAM memory cell configuration with a vertical storage capacitor with a ferroelectric or paraelectric storage dielectric is known. For producing the storage capacitor, a dielectric layer for the storage dielectric is created over a large surface area. The dielectric layer is then structured, forming first and second electrodes for the storage capacitors.
According to Published, Non-Prosecuted German Patent Application DE 195 43 539 A, a ferroelectric material for nonvolatile memories is used as the storage dielectric, because this material has spontaneous polarization that exists even in the absence of an external electrical field. Paraelectric material, conversely, is used in DRAM applications, in which a refresh cycle is provided.
In practice at the moment, only cell sizes of about 9F
2
per memory cell are attainable using the known concepts for memory cells that contain one selection transistor and a storage capacitor (such as a DRAM). The goal, beginning with the 1-gigabit generation, is a cell size of 8F
2
, where F=0.18 &mgr;m.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a memory cell configuration and production process therefor which overcome the above-mentioned disadvantages of the prior art devices and methods of this general type, which has a tightly packed memory cell configuration that has preferably ferroelectric memory cells and that can be produced easily and reliably, and a corresponding production process.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory cell configuration with a plurality of one of ferroelectric memory cells and dynamic memory cells, including:
a semiconductor substrate having a main face;
alternating trenches having trench bottoms and lands having land ridges extending parallel in a longitudinal direction of the main face and formed in the semiconductor substrate;
a channel stop layer buried in the lands for dividing the semiconductor substrate into a lower region that includes the trench bottoms and an upper region that includes the land ridges;
trench channel stop regions disposed in the trench bottoms in the lower region of the semiconductor substrate;
first planar selection transistors disposed in the trenches and separated from each other by the trench channel stop regions disposed between adjacent pairs of the first planar selection transistors;
land channel stop regions disposed along the land ridges in the upper region of the semiconductor substrate;
second planar selection transistors disposed along the lands and separated from each other by the land channel stop regions disposed between adjacent pairs of the second planar selection transistors, the first planar selection transistors and the second planar selection transistors have respective source regions, gate regions, channel regions and drain regions being offset longitudinally from one another such that the source regions and the drain regions of the first planar selection transistors and the second planar selection transistors alternate in a transverse direction in the main face of the semiconductor substrate;
isolated word lines extending in the transverse direction along the main face of the semiconductor substrate for triggering the gate regions of the first planar selection transistors and the second planar selection transistors;
isolated bit lines extending in an oblique direction along the main face of the semiconductor substrate and connected to the source regions of the first planar selection transistors and the second planar selection transistors;
capacitor contacts; and
a plurality of capacitors, one of the plurality of capacitors connected to each of the drain regions of an associated one of the first planar selection transistors and the second planar selection transistors via the capacitor contacts.
The memory cell configuration of the invention with preferably ferroelectric memory cells has the advantage over the known memory cell configurations that it has an attainable minimum cell size of less than 6F
2
with planar transistors that are disposed both on trench bottoms and on land ridges. The memory cell configuration is simple to produce and does not require STI-isolation trenches as previous concepts do.
In contrast to the usual process for producing a DRAM with a stacked capacitor, the bit line in the memory cell configuration of the invention no longer extends perpendicular to the word line, but rather at an angle of typically 60° to it. For connecting the bit lines for the transistors, the bit lines are raised to the original semiconductor substrate height with

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