Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2001-09-19
2003-06-17
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C257S145000, C365S158000, C365S173000
Reexamination Certificate
active
06579729
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a memory cell configuration with memory elements having a layer structure with a magnetoresistive effect.
Layer structures with a magnetoresistive effect are known from the technology analysis titled “XMR-Technologien, Technologiefrüherkennung [XMR Ttechnologies, Technology Detection At An Early Stage]”, author Stefan Mengel, published by VDI Technologiezentrum Physikalische Technologien. Depending on the construction of the layer structure, a distinction is made between a giant magnetoresistance (GMR) element, a tunneling magnetoresistance (TMR) element, an anisotropic magnetoresistance (AMR) element and a colossal magnetoresistance (CMR) element.
The term GMR element is used by experts for layer structures that have at least two ferromagnetic layers and a nonmagnetic, conductive layer disposed in between and exhibit the so-called giant magnetoresistance effect, that is to say a large magnetoresistive effect in comparison with the anisotropic magnetoresistance effect. The GMR effect encompasses the fact that the electrical resistance of the GMR element is dependent on whether the magnetizations in the two ferromagnetic layers are oriented in a parallel or antiparallel manner.
Tunneling magnetoresistance layer structures have at least two ferromagnetic layers and an insulating, nonmagnetic layer disposed in between. In this case, the insulating layer is so thin that a tunneling current occurs between the two ferromagnetic layers. The layer structures likewise exhibit a magnetoresistive effect that is caused by a spin-polarized tunneling current through the insulating, nonmagnetic layer disposed between the two ferromagnetic layers. In this case, too, the electrical resistance of the TMR element is dependent on whether the magnetizations in the two ferromagnetic layers are oriented in a parallel or antiparallel manner.
The AMR effect is manifested in the fact that the resistance in magnetized conductors is different parallel and perpendicular to the magnetization direction. It is a volume effect and thus occurs in single ferromagnetic layers.
A further magnetoresistance effect, which is called a colossal magnetoresistance effect because of its magnitude (&Dgr;R/R=100 to 400% at room temperature), requires a high magnetic field for changing over between the magnetization states on account of its high coercive forces.
U.S. Pat. No. 5,640,343 describes a so-called magnetoresistive random access memory (MRAM) cell configuration in which memory cells are disposed between two layers of metallic lines disposed one above the other. The memory cells each have a diode and a memory element connected in series therewith. The memory element has a layer structure with a magnetoresistive effect. The diode is a pn diode or a Schottky diode which contains silicon. The layer structure of the memory element and the layer structure of the diode are disposed above one another. The metallic lines of the first layer run parallel to one another. The metallic lines of the second layer run parallel to one another and perpendicularly to the metallic lines of the first layer. The memory cells are in each case connected between a metallic line of the first layer and a metallic line of the second layer. The layer structure of the memory element contains two ferromagnetic layers and an insulating layer disposed in between. The electrical resistance of the memory element depends on whether the magnetization directions of the two ferromagnetic layers are parallel or antiparallel to one another. In order to write an information item to a memory cell, currents are impressed on the metallic lines that are connected to the memory cell. In this case, voltages are chosen such that no current flows through the memory cell. The magnetic fields generated by the currents accumulate in the region of the memory cell in such a way that the magnetization of one of the two magnetic layers is oriented in the magnetic field. The magnetization direction of the other ferromagnetic layer remains unchanged. The orientation represents the information item. In order to read out the information item, the voltage of the metallic line that is connected to the diode is lowered and the voltage on the metallic line that is connected to the memory element is increased. The same voltage is present on metallic lines that are connected to the remaining memory elements as on the metallic line which is connected to the diode of the memory cell to be read. The same voltage is present on the metallic lines that are connected to the remaining diodes as on the metallic line which is connected to the memory element of the memory cell to be read. On account of the diodes in the memory cells, current can only flow through the memory cell to be read. The current has two discrete values depending on the information stored on the memory cell, which values correspond to two magnetization states of the memory element.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a memory cell configuration and a method for fabricating it which overcomes the above-mentioned disadvantages of the prior art devices and methods of this general type, which can be fabricated with an increased packing density in comparison with the prior art.
With the foregoing and other objects in view there is provided, in accordance with the invention, a memory cell configuration. The memory cell configuration contains at least three layers of metallic lines, and two layers of memory cells disposed in conjunction with the metallic lines alternately one above another. The memory cells each have a diode and a memory element connected in series with the diode. The memory element has a layer structure with a magnetoresistive effect. The diode has a layer structure containing at least two metal layers and an insulating layer disposed in between the two metal layers. The layer structure of the memory element and the layer structure of the diode are disposed above one another. The metallic lines in each of the three layers run parallel to one another. The metallic lines of mutually adjacent ones of the three layers run transversely with respect to one another, and the memory cells are in each case connected between one of the metallic lines of one of the three layers and one of the metallic lines of an adjacent one of the three layers.
The problem is furthermore solved by a method for fabricating a memory cell configuration, in which a first layer of metallic lines that run parallel to one another is produced. A first layer of memory cells is produced above the first layer of metallic lines in such a way that the memory cells of the first layer are connected to the metallic lines of the first layer. A memory element and a diode connected in series therewith are in each case produced for the memory cells of the first layer. For the diode, a layer structure is produced which contains at least two metal layers and an insulating layer disposed in between. A layer structure with a magnetoresistive effect is produced for the memory element. The layer structure of the memory element and the layer structure of the diode are produced above one another. A second layer of metallic lines, which run parallel to one another and transversely with respect to the metallic lines of the first layer, is produced above the first layer of memory cells in such a way that the memory cells of the first layer are in each case connected between a metallic line of the first layer and a metallic line of the second layer. Memory cells of a second layer that are constructed in accordance with the memory cells of the first layer are produced above the second layer of metallic lines. A third layer of metallic lines, which run parallel to one another and transversely with respect to the metallic lines of the second layer, is produced above the second layer of memory cells in such a way that the memory cells of the second layer are in each case connected between a metallic line of the second layer and a meta
Goebel Bernd
Schwarzl Siegfried
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
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