Memory cell circuit having radiation hardness

Details Memory cell circuit having radiation hardness Memory cell circuit having radiation hardness

1986-08-26

1989-05-23

Hecker, Stuart N.

Static information storage and retrieval

Hardware for storage elements

Shields

365149, 365154, 36518901, G11C 700, G11C 1140, G11C 1124

Patent

active

048336440

ABSTRACT:
A memory cell circuit has a pair of inverters and a means, such as gate-drain coupled capacitors, for providing a greater voltage difference at MOS transistor gates during radiation than an initial value. This tends to preserve the latch logic state and thus prevent a change in logic state during radiation.

REFERENCES:
patent: 3990056 (1976-11-01), Luisi et al.
patent: 4130892 (1978-12-01), Gunckel II et al.
patent: 4149268 (1979-04-01), Waters
patent: 4314359 (1982-02-01), Kato et al.
patent: 4538244 (1985-08-01), Sugo et al.
patent: 4590508 (1986-05-01), Hirakawa et al.
patent: 4760557 (1988-07-01), Stewart et al.
Herbert et al. "SOS Test Structures for Measurement of Photocurrent Sources and Upset Dose Rates in Memories", DNA/Aerospace Corp. Workshop on Test Structures for Radiation Hardening and Hardness Assurance, Feb. 19, 1986.

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