Memory cell array with LOCOS free isolation

Details Memory cell array with LOCOS free isolation Memory cell array with LOCOS free isolation

1996-10-17

1998-04-14

Yoo, Do Hyun

Static information storage and retrieval

Floating gate

Particular connection

365 51, 365 63, 36518501, 257315, 257321, G11C 1134

Patent

active

057401055

ABSTRACT:
An EPROM or flash EEPROM, which has an array of single-transistor, stacked-gate, memory cells. Active areas for transistor elements are in columns up and down the array, with columns being isolated by thick field oxide strips (220). Word lines (236) and source lines (212) run across the array. Bit lines (216) run along the active area columns to connect transistor drains (218). Bit lines are perpendicular to word lines. Each stacked gate includes a control gate (232) and a floating gate (230), with the latter having a top portion (230b) and a bottom portion (230a) that are separately deposited and etched. The bottom portion (230a) is etched in strips along the active area columns, and define the gate width of each cell. The top portion (230b) overlaps the bottom portion (230a) to improve capacitance between control gate (232) and floating gate (230).

REFERENCES:
patent: 5089866 (1992-02-01), Iwasa
patent: 5278438 (1994-01-01), Kim et al.
patent: 5282160 (1994-01-01), Yamagata
patent: 5291439 (1994-03-01), Kauffmann et al.
patent: 5469383 (1995-11-01), McElroy et al.

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