Memory cell array having continuous-strip field-oxide regions

Details Memory cell array having continuous-strip field-oxide regions Memory cell array having continuous-strip field-oxide regions

1994-06-24

1995-11-21

Nelms, David C.

Static information storage and retrieval

Floating gate

257315, 257316, 257389, 257396, G11C 1134

Patent

active

054693837

ABSTRACT:
A CMOS memory cell array and a method of forming it, which avoids problems caused by field oxide corner-rounding. A moat pattern defines alternating columns of active areas and field oxide regions. A source line pattern defines rows of source lines. Silicon dopant is implanted in areas not covered by the source line pattern to form buried n+ source lines. The field oxide regions are formed in areas not covered by the moat pattern. Subsequent fabrication steps may be in accordance with conventional CMOS fabrication techniques.

REFERENCES:
patent: 5323039 (1994-06-01), Asano et al.

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