Memory cell array divided type semiconductor memory device

Details Memory cell array divided type semiconductor memory device Memory cell array divided type semiconductor memory device

1992-03-09

1994-07-12

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

Plural blocks or banks

36518901, 365207, G11C 800, G11C 700

Patent

active

053294947

ABSTRACT:
The memory device of this invention includes a plurality of memory cell blocks each having a plurality of memory cells disposed in a matrix form. A memory cell selector selects a predetermined number of the memory cells in each memory cell block in accordance with external address signals. A sense amplifier unit amplifies data read from the selected memory cells for data read. A data output unit outputs the data amplified by the sense amplifier unit. A block selector selects a desired one or more of the memory cell blocks as data write blocks for data write. A data write unit writes data in the selected memory cells in the selected blocks. A sense amplifier controller supplies, during the data write, a signal to the sense amplifier unit to make the sense amplifier unit inactive, and during the data read supplies a signal to the sense amplifier unit to make the sense amplifier unit active.

REFERENCES:
patent: 4796234 (1989-01-01), Itoh et al.
patent: 4879692 (1989-11-01), Tokushige
patent: 4931994 (1990-01-01), Matsui et al.

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