Memory cell array architecture for random access memory device

Details Memory cell array architecture for random access memory device Memory cell array architecture for random access memory device

1999-05-03

2000-08-01

Mai, Son

Static information storage and retrieval

Interconnection arrangements

365149, 257211, 257296, G11C 506, H01L 27108

Patent

active

060976217

ABSTRACT:
A memory cell array architecture (300) for memory cells having a 6F.sup.2 area, where F is a minimum feature size, is disclosed. The array architecture (300) includes active areas (302a-302n) arranged into even columns and odd columns. The active areas (302a-302n) each include a central portion (306) and are separated from one another within a column by column spacing structures (308). The active areas of even columns are offset from those of odd columns so that the central portion the even column active areas are aligned, in the row direction, with the column spacing structures of the odd columns. This arrangement allows bit line contacts (312a-312g) to be formed at the central portions with less restrictive alignment constraints. Two storage node contacts (316a-316t) are also formed to each active area (302a-302n). A novel lithography mask for improved creation of the storage node contacts is also disclosed.

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