Static information storage and retrieval – Floating gate – Particular connection
Patent
1993-07-08
1998-02-17
Clawson, Jr., Joseph E.
Static information storage and retrieval
Floating gate
Particular connection
365104, 36523006, G11C 1606
Patent
active
057198063
ABSTRACT:
A memory cell array of high density, enabling high speed read-out. Diffusion wires columnwise extending in a block in the array serve as bit and ground lines alternately disposed and gate wires parallel to each other are formed perpendicularly to the diffusion wires. Channels are defined in regions between the adjacent diffusion wires under the gate wires, whereby MOS transistors are formed. A memory circuit has such a memory cell array and a decoder connected thereto. Paired adjacent bit lines are connected through a bit line select transistor to a contact, and the contact is connected through a metal line columnwise connecting between blocks, via a transistor of decoder to a main bit line. Paired adjacent ground lines are connected through a ground line select transistor to a contact for ground line, and the contact is connected through a metal line columnwise connecting between blocks, via a transistor of decoder to a main ground line.
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Matsuo Masahiro
Yamane Masatoshi
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