Memory cell architecture utilizing a transistor having a dual ac

Static information storage and retrieval – Floating gate – Particular connection

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Details

36518501, 365161, 365104, 365175, G11C 1604

Patent

active

059128402

ABSTRACT:
A memory cell architecture utilizing a dual access gate and dual wordlines is disclosed. The cell is comprised of a first transistor connected between a digitline and a cellplate. The transistor is responsive to a read wordline to enable the cell to be read. An active device, such as a second transistor, is provided for modifying at least one conductive characteristic of the first transistor according to the state of a signal on the digitline. The conductive characteristic that is modified may be, for example, the threshold voltage or the transistor's channel resistance. Modification of the first transistor's characteristics is representative of writing information to the memory cell. A circuit structure for implementing the circuit architecture is also disclosed together with a method of operating a memory cell.

REFERENCES:
patent: 3849767 (1974-11-01), Shirato
patent: 5089866 (1992-02-01), Iwasa
patent: 5511020 (1996-04-01), Hu et al.
patent: 5569946 (1996-10-01), Hong
patent: 5597749 (1997-01-01), Iguchi
patent: 5600593 (1997-02-01), Fong

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