Memory cell architecture

Static information storage and retrieval – Read only systems

Reexamination Certificate

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C365S100000

Reexamination Certificate

active

07995368

ABSTRACT:
Embodiments of the present invention disclose a memory architecture for optimizing memory performance and size. Memory optimization is realized by configuring the memory to a particular logic state; that is, restricting memory data storage to either logic “0” or “1.” The opposite logic state, “1” or “0,” can be available through initialization and, therefore, may be presumed. Accordingly, the presumed, initialized logic state is available unless the configured logic state in memory changes the initialized data during memory access. Memory size reduction is realized by restricting physical memory to contain only cells that store data. Memory size can be further reduced by eliminating redundant data rows and columns. By reducing memory size, processing speed can be enhanced and power consumption reduced relative to conventional memory structures.

REFERENCES:
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patent: 6587394 (2003-07-01), Hogan
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patent: 2006/0187697 (2006-08-01), Khanuja
A. Moshovos et al., “A Case for Asymmetric-Cell Cache Memories,” IEEE Transactions on Very Large Scale Integration (VL:SI) Systems, vol. 13, No. 7, Jul. 2005, pp. 877-881.
N. Azizi et al., “An Asymmetric SRAM cell to lower Gate Leakage,” IEEE Computer Society, 0-7695-2093-6/04 2004 IEEE.
Y. Yibin, et al., “Evaluation of Differential vs. Single-Ended Sensing and Asymmetric Cells in 90nm Logic Technology for On-Chip Caches,” ISCAS 2006, pp. 963-966.
N. Azizi, et al., “Low-leakage Asymmetric-Cell SRAM,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, No. 4, Aug. 2003, pp. 701-715.

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