Memory cell allowing write and erase with low voltage power supp

Details Memory cell allowing write and erase with low voltage power supp Memory cell allowing write and erase with low voltage power supp

1998-03-06

2000-01-11

Nelms, David

Static information storage and retrieval

Floating gate

Particular connection

36518517, G11C 1604

Patent

active

060143282

ABSTRACT:
In a nonvolatile semiconductor memory device, a memory cell array includes memory cell transistors and cell select transistors corresponding to the memory cell transistors, respectively. A memory cell SG decoder supplies a potential to a cell select line corresponding to the selected row. The cell select transistor opens and closes a conduction path of a current flowing between a bit line and a source line through the memory cell transistor in accordance with the potential on the cell select line. As a result, an influence by a leak current flowing from the unselected memory cell transistor in a read operation is suppressed.

REFERENCES:
patent: 4442510 (1984-04-01), Priel et al.
patent: 5471422 (1995-11-01), Chang et al.
patent: 5576989 (1996-11-01), Kowalski
patent: 5592001 (1997-01-01), Asano
"A High Density Floating-Gate EEPROM Cell," J.R. Yeargain, et al., IEDM 81, pp. 24-27.

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