Memory card refresh buffer

Details Memory card refresh buffer Memory card refresh buffer

1989-12-13

1993-03-09

Eng, David Y.

Boots, shoes, and leggings

36424691, 3649649, 364DIG2, G06F 1300, G11C 1300

Patent

active

051931656

ABSTRACT:
A data processing network includes multiple processing devices, one or more memory cards in main storage, and a shared interface for processor access to main storage. Each of the memory cards includes dynamic random access memory arrays which require a periodic refresh pulse. To provide refresh pulses, each of the memory cards includes a programmable register, a counter receiving clock pulses, and a comparator. The comparator generates a request pulse each time the output from the pulse counter equals a selected value provided by the register. The register is programmable to controllably adjust the selected value, and thus select the frequency at which refresh request pulses are generated by the comparator. The memory card further includes a buffer for receiving the refresh request pulses and generating a refresh request responsive to each pulse. Responsive to the refresh request, a memory array control circuit either provides a refresh signal to the arrays, or stores the refresh request, depending on whether the arrays are busy with an external request. However, when stored requests accumulate to a predetermined threshold, the external request is interrupted and a refresh signal is provided to the arrays.

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IBM Technical Disclosure Bulletin, "Minimal Interference Refresh", vol. 30, No. 10, Mar. 1988, pp. 201-203.
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C. J. Gerardin and J. P. Levis, IBM Technical Disclosure Bulletin, vol. 16, No. 3, Aug. 1973, pp. 934-936.
J. A. Buettner, T. L. Crooks, L. J. Johnson and L. F. Saunders, IBM Technical Disclosure Bulletin, vol. 23, No. 4, Sep. 1980, pp. 1592-1602.

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