Memory card having a plurality of EEPROM chips

Static information storage and retrieval – Floating gate – Particular biasing

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Details

36518511, 365200, 365 52, 36523003, G11C 1134

Patent

active

055131387

ABSTRACT:
A data writing operation of a memory card is performed from a first EEPROM chip. Writing commands are given every time data in a memory block unit are completely transferred. Each of four EEPROM chips is performing the writing operation when data of the four EEPROM chips are completely written to the memory card. A systematic side waits for the next data transfer in view of an RDY/BSY signal of the memory card. The data writing operation from the systematic side to each of the four EEPROM chips is sequentially changed by monitoring an RDY/BSY1 signal of the first EEPROM chip. In this construction of the memory card, data can be preferably written and read from the memory card at a high speed.

REFERENCES:
patent: 5303198 (1994-04-01), Adachi et al.
patent: 5388248 (1995-02-01), Robinson et al.

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