Memory card device including a clock generator

Static information storage and retrieval – Hardware for storage elements

Reissue Patent

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Details

C365S233100, C365S185080, C365S185330

Reissue Patent

active

RE040147

ABSTRACT:
Disclosed herein is a card having a controller and a clock control circuit. The controller incorporates a core logic, and the clock control circuit incorporates a PLL. When a card becomes idle to wait for commands, the clock control circuit stops the supply of a clock signal to the core logic. The clock control circuit can operate in two clock control modes. In the first clock control mode, the circuit stops the PLL. In the second clock control mode, the circuit shuts off the clock signal to be supplied from the PLL to the controller.

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Notification of Reasons for Rejection issued by the Japanese Patent Office on Apr. 25, 2006, for Japanese Patent Application No. 2000-300446, and English-language translation thereof.

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