Memory card device including a clock generator

Details Memory card device including a clock generator Memory card device including a clock generator

2001-09-18

2002-06-18

Phan, Trong (Department: 2818)

Static information storage and retrieval

Hardware for storage elements

C365S233100, C365S185330

Reexamination Certificate

active

06407940

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory card device that can be used in various types of electronic apparatuses. More particularly, the invention relates to a memory card device that includes a clock generator.
2. Description of the Related Art
In recent years, various portable electronic apparatuses have been developed. Among them are personal computers, PDAs, digital cameras, mobile telephones. Memory cards, which are removable memory devices, are used in these portable electronic apparatuses. Two types of memory cards are known. The first is a PCMCIA card (generally known as “PC card”). The second is a SD (Secure Digital) card that is smaller than the PCMCIA card.
The SD card incorporates a flash memory. It is small and can yet store as much data as desired and operate at as high a speed as desired. The SD card has an improved 9-pin interface. Of the nine pins, four serve to transfer data to the host apparatus. Despite a few interface pins it has, the SD card can transfer data in sufficient performance.
Recently it is demanded that power consumption be reduced in small memory cards typified by SD cards. To reduce power consumption in an electronic device, the supply of clock signals to the internal core logic units of the electronic device may be stopped as is known in the art. In a device including a PLL (Phase Locked Loop), more power consumption can be reduced by stopping the PLL operation itself than by stopping the supply of clock signals from the PLL to the internal core logic units.
Once the PLL operation is stopped to set the device into power-saving mode, however, it will take much time to set the device return into the normal operating mode. This is because the PLL cannot generate stable clock signals for some time after it starts operating again. In other words, the internal core logic units cannot operate until the clock signals become sufficiently stable.
Particularly, a memory card that incorporates a nonvolatile memory such as a flash EEPROM cannot respond fast, because it takes a relatively long time to access the nonvolatile memory. To make the matter worse, the internal core logic units will need a long time to restart their operations once the PLL provided in the device is stopped to save power. The memory card inevitably responds even more slowly.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a memory card device that can operate fast and can yet save power sufficiently.
To achieve the object, a memory card device is designed to be removably inserted in a host apparatus, the memory card device comprises: a nonvolatile memory device; a controller configured to execute commands supplied from the host apparatus, thereby to write data into, and read data from, the nonvolatile memory; a clock signal generator that includes a PLL configured to generate a clock signal to be supplied to the controller; and a clock control unit configured to operate in a first clock control mode, wherein the clock control unit stops the operation of the PLL, if the controller becomes idle while the memory card device is in a first state in which the memory card device receives a command concerning an access to the nonvolatile memory device from the host apparatus, and configured to operate in a second clock control mode, wherein the clock control unit shuts off the clock signal outputted from the PLL, if the controller becomes idle while the memory card device is in a second state in which the memory card device needs not to receive the command concerning an access to the nonvolatile memory device from the host apparatus.
In the memory card device, the clock control unit stops supplying the clock signal to the controller when the controller becomes idle to wait for commands. The supply of the clock signal can be stopped in two modes, i.e., the first clock control mode for stopping the operation of the PLL, and the second clock control mode for shutting off the clock signal outputted from the PLL. The clock control mode is switched, from the first to the second, or vice versa, in accordance with whether the current state of the card is a state in which the card device receives a command concerning an access to the nonvolatile memory device from the host apparatus.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.


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patent: 2000-66654 (2000-03-01), None

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