Memory card, computer system and method of operation for differe

Details Memory card, computer system and method of operation for differe Memory card, computer system and method of operation for differe

1993-11-17

1996-01-30

Beausoliel, Jr., Robert W.

Excavating

39518203, 371 401, G06F 1110

Patent

active

054886910

ABSTRACT:
The present invention relates to a computer system and method of using the same in which add-on memory cards are provided which have error correction code logic on the card and logic to do partial writes of data words. The system has a central processing unit (CPU), and a BUS interconnecting the CPU and the add-on memory cards which are configured to write data and read data from the add-on memory. The system is further configured (either within the CPU or as a separate function) to generate parity bits associated with each of the bytes of data the CPU writes to the add-on memory and to read parity bits associated with data the CPU reads from the add-on memory and regenerate new parity bits and compare the newly generated parity bits with the original parity bits to detect data errors on data read from the add-on memory. The add-on memory has ECC logic to identify any byte having a single bit error in the data bytes or the parity bits written by the CPU to the add-on memory and to correct all single bit errors in data read from the add-on memory to the CPU.

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