Memory card

Details Memory card Memory card

2001-06-29

2003-12-30

Le, Thien M. (Department: 2876)

Registers

Records

Conductive

C235S380000, C235S441000

Reexamination Certificate

active

06669099

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory card used with a host system, such as an information processing device, connected thereto.
2. Description of the Related Art
In general, a memory card is used while being connected to a host system which processes information. The memory card is connected to the host system such that the host system can store, read, or overwrite data in the memory card. For such a memory card, for example, a flash memory is used. Only when the host system checks a device ID stored in the memory card and determines that the memory card is compatible with the host system, the host system can read, write, or delete data in the memory card.
FIG. 3
is a block diagram illustrating a first exemplary configuration of a conventional memory card. In
FIG. 3
, a memory card
101
includes a component memory section
102
in which data can be overwritten, and a card control section
103
which includes a bus buffer, an address decoder, etc.
The component memory section
102
includes a command control-type memory section for storing a device ID. The device ID includes a manufacturer code (e.g., a code assigned to Sharp K.K. is B0H) and a device code (e.g., a code assigned to a 16Mb device is D0H, where every product type of device has its own device code).
The card control section
103
controls the component memory section
102
by using the address decoder, etc. A host system
100
outputs an address signal and a command signal to the memory card
101
through an address bus AB and a data bus DB, respectively. Based on these signals, the host system
100
writes data to a prescribed address in the component memory section
102
or reads data corresponding to a prescribed address from the component memory section
102
.
When a reset signal RESET is input to the card control section
103
, the card control section
103
outputs a reset signal RESET′ to the component memory section
102
to put the component memory section
102
into a reset state. Note that there are generally two types of memory cards. A memory card of the first type is put into a reset state by a high-level signal. A memory card of the second type is put into a reset state by a low-level signal. In this conventional example, the memory card is put into a reset state by a high-level signal.
When a write enable signal WE# which is a write selection signal, a chip enable signal CE# which is a chip selection signal, and an output enable signal OE# which is a data output selection signal are input from the host system
100
to the card control section
103
, the card control section
103
outputs a write enable signal WE#′, a chip enable signal CE#′, and an output enable signal OE#′, respectively, to the component memory section
102
. The symbol “#” indicates the inversion of a signal level, which means that a signal is active when low. This allows the component memory section
102
to be put into an active state by a low-level signal. The card control section
103
outputs the address signal and the command signal from the host system
100
to the component memory section
102
through the address bus AB and the data buses DB, DB′, respectively. Based on these signals, the card control section
103
controls reading or writing of data corresponding to an address in the component memory section
102
which is designated by the address signal. In the case where data can be written in the component memory section
102
, the write enable signal WE# is at a low level.
In the above described configuration, the host system
100
reads a device ID from the memory card
101
to check the device ID and to determine whether or not the memory card
101
is compatible with the host system
100
in the manner described below.
When the component memory section
102
is in a state such that data can be read therefrom (“read array mode”), the chip enable signal CE#, the write enable signal WE#, and the output enable signal OE#, which are output from the host system
100
, are set to an active state (low level), an active state (low level), and an inactive state (high level), respectively.
Next, the host system
100
outputs an ID transmission request command, for example, 9090H, to the card control section
103
through the data bus DB, and then the card control section
103
outputs the ID transmission request command 9090H to the component memory section
102
through the data bus DB′.
The component memory section
102
recognizes the ID transmission request command 9090H output from the card control section
103
, and outputs the device ID stored in the component memory section
102
to the card control section
103
through the data bus DB′. The card control section
103
outputs the device ID received from the component memory section
102
to the host system
100
through the data bus DB.
The host system
100
checks the device ID output from the memory card
101
to determine whether or not the memory card
101
is compatible with the host system
100
. If the memory card
101
is determined to be compatible with the host system
100
, operations such as reading or writing of data can be performed between the memory card
101
and the host system
100
according to command signals output from the host system
100
. If the host system
100
determines otherwise, operations cannot be performed between the memory card
101
and the host system
100
according to command signals output from the host system
100
.
The command signal is not limited to the ID transmission request command 9090H described above. A flash memory card which is available from Sharp K.K. accepts a reset command FFFFH, a status register read command 7070H, a status register clear command 5050H, a deletion command D0D0H, a write set-up command 4040H, a write command 1010H, etc.
In a memory card with simplified circuitry, the function of the card control section
103
may be limited to only a decode function which uses an address signal. In such a memory card, a bus width of the data bus DB′ between the card control section
103
and the component memory section
102
may be fixed to 16 or 8 bits, and the component memory section
102
and the host system
100
may be directly connected to each other through the data bus DB. In this case, each of the signal lines for the write enable signal WE#, the output enable signal OE#, and the reset signal RESET between the host system
100
and the card control section
103
is directly connected to each of the corresponding signal lines for the write enable signal WE#′, the output enable signal OE#′, and the reset signal RESET′ between the card control section
103
and the component memory section
102
without passing through the card control section
103
.
When the component memory section
102
includes a plurality of memories, the card control section
103
has a function of decoding an upper bit portion of an address signal to select a memory with a corresponding address to the address signal.
In a memory card having the above-described conventional configuration, there is a case where the host system
100
checks the device ID output from the memory card
101
and determines that the memory card
101
is not compatible with the host system
100
even though they have compatibility of an algorithm with each other. In this case, operations between the host system
100
and the memory card
101
cannot be performed according to a command signal. As an example of solving such a problem, Japanese Laid-Open publication No. 11-328009 proposes “A MEMORY CARD AND A METHOD OF DETERMINING OPERATING COMPATIBILITY USING SUCH A MEMORY CARD”.
FIG. 4
illustrates a configuration of such a memory card.
FIG. 4
is a block diagram illustrating a second exemplary configuration of a conventional memory card. In
FIG. 4
, a memory card
201
includes an address decoder
202
, first and second memories
203
and
204
, a command decoder

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