Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-08-11
2002-02-26
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185110, C365S185330
Reexamination Certificate
active
06351412
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to techniques adapted advantageously to a memory device in which data is to be stored along with error correcting codes. More particularly, the invention relates to techniques utilized effectively in a nonvolatile semiconductor memory such as a flash memory and to an IC card incorporating that memory.
There exists a nonvolatile semiconductor memory called a flash memory capable of having its stored data erased electrically in units of predetermined blocks. In the form of memory cells, the flash memory employs nonvolatile storage elements each made of a MOSFET of a two-layer gate structure having a control gate and a floating gate. One transistor constitutes one memory cell.
In such a flash memory, as shown in
FIG. 8A
, a threshold voltage of a nonvolatile memory cell is driven High (e.g., to logical “1”) by applying a high voltage (e.g., 16V) via a word line to a control gate CC of the cell, by applying ground potential (0V) via a bit line to a drain D of the cell (source S is left open), and by injecting a negative charge to a floating gate FG of the cell. The threshold voltage of the cell is brought Low (e.g., to logical “0”), as shown in
FIG. 8B
, by applying a negative voltage (−16V) via the word line to the control gate CG, by applying ground potential to the drain D and source S, and by electrically discharging the floating gate FG. In the manner outlined above, one bit of data is stored in one memory cell.
Memory cells having different threshold voltages set therein allow different drain currents to flow therethrough depending on the voltages applied to the control gates. When data are to be read out, the difference between drain currents is taken advantage of. That is, an intermediate voltage between the two threshold voltages is applied to the control gate of a given cell so as to detect its drain current quantity allowing the stored data to be judged as “1” or “0.”
In the flash memory, write and read operations are carried out illustratively in units of sectors That is, a write or a read operation is performed simultaneously on a row of memory cells sharing a word line. An erase operation is executed simultaneously on a block, i e., on a plurality of sectors sharing a well region. In describing embodiments of this invention below, these specifics are assumed but not specifically referred to.
Generally, the flash memory may submit received data to an error correction coding process based on the Hamming code, Reed-Solomon code or the like so as to store the data together with redundant codes At the time of data read operations, the flash memory is often arranged to output automatically corrected data using error correcting codes.
SUMMARY OF THE INVENTION
In a conventional flash memory having an error correcting function, as shown in
FIG. 7
, desired data are typically read from a memory array into a data register or the like and transferred successively from there to an error correcting circuit whereby syndromes are formed indicating whether any error has occurred. The read-out data in the data register are again transferred successively to the error correcting circuit for error correction before being sent to the outside.
In the above process, it takes a total time period of “tACC+tSYN+tOUT” for an external device such as a microprocessor that accessed the memory to acquire all target data therefrom. In the above expression, “tACC” denotes the period from the time a read request is issued to the memory until the data in the memory cells at the specified address are latched into the data register; “tSYN” represents the time it takes to form syndromes; and “tOUT” stands for the time required to output all data from the data register while the data are being corrected.
In more specific example, the time “tSYN” is about 102 &mgr;s for a memory whose sectors are constituted by 2 kilobytes each and whose one-byte transfer cycle is 50 ns. Even if no error exists in the read-out data, the time “tSYN” is always included as an overhead. Moreover, the probability of any read-out data actually containing an error is considerably low. As a result, the read time is often prolonged unnecessarily.
It is therefore an object of the present invention to provide techniques allowing a nonvolatile memory device with an error correcting function to shorten the time required to read data therefrom.
It is another object of the present invention to provide a nonvolatile memory device capable of indicating externally the presence or absence of error in the output data as well as the status of data error correction.
Other objects, features and advantages of the invention will become more apparent upon a reading of the following description and appended drawings.
In a broad outline, the present invention envisages providing a nonvolatile memory device (a nonvolatile semiconductor memory or a memory system comprising that memory) for outputting read-out data (uncorrected) while simultaneously generating syndromes. After the syndrome formation, the inventive memory device outputs an error status signal (ERR) indicating whether any error has occurred and may again output read-out data (corrected) depending on the presence or absence of a request (SC) from the outside.
In carrying out the invention more specifically and according to one aspect thereof, there is provided a memory device comprising: a memory array made of a plurality of nonvolatile memory cells arranged in matrix fashion, each of the nonvolatile memory cells being furnished with a control gate and a floating gate and having a threshold voltage corresponding to data held therein; and an error correcting circuit which receives data read from a plurality of memory cells in the memory array and which corrects any error included in the read-out data: wherein the read-out data are sent in a predetermined block from the memory array to the error correcting circuit while being externally output simultaneously; wherein the error correcting circuit externally outputs, either upon completion of the data output or immediately thereafter, an error status signal indicating whether any error is included in the read-out data; and wherein upon detection of any error in the read-out data of the predetermined block from the memory array, the error correcting circuit corrects the error.
With the above structure, the read-out data are output during syndrome formation by the error detection circuit. If the error status signal indicates the absence of any error, the obtained data are thus immediately processed as effective read-out data. This structure drastically reduces the time required to read data from the memory device.
In one preferred structure according to the invention, the memory device may further comprise a data holding element for holding data read in a predetermined block from a plurality of memory cells in the memory array, wherein, if any error is found included in the read-out data, the data holding element causes the read-out data held therein to be corrected by the error correcting circuit before having the corrected data output externally. In case of an error, this preferred structure causes the same data to be fed immediately from data registers to the error correcting circuit for error correction without accessing the memory array anew.
In another preferred structure according to the invention, the memory device may further comprise an element for outputting correction status information if any error in the read-out data has been corrected by the error correcting circuit. The structure allows a user to know that the obtained data are corrected data.
In a further preferred structure according to the invention, the correction status information may include information indicating whether the error in the read-out data has been corrected properly. This feature allows the user to know whether the detected error has been corrected adequately.
In an even further preferred structure according to the invention, the data read uncorrected from the memory array and the c
Katayama Kunihiro
Nakamura Kazuo
Nozoe Atsushi
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Hoang Huan
Lam David
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