Memory capacity detection apparatus and electronic applied measu

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364970, 3649705, 371 211, G06F 1206

Patent

active

050035061

ABSTRACT:
A RAM the capacity of which is to be detected is constituted by 2.sup.N memory blocks each having a predetermined memory capacity. An address signal representing an existing memory capacity can be fed to the RAM. An address controller designates a predetermined address for each block of the RAM. A code write section sequentially writes a detection code at the predetermined address in each block of the RAM. A code readout section reads out the detection code from the predetermined address of the first block of the RAM designated by the address controller. A code comparator sequentially compares the detection code read out by the code readout section with a detection code last written by the code write section, so as to detect whether there is a coincidence therebetween, and, when a coincidence is obtained, the comparator is able to detect the capacity of the entire RAM based on the coincident detection code.

REFERENCES:
patent: 4592011 (1986-05-01), Mantellina et al.
patent: 4860252 (1989-08-01), Sykora

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