Memory cache with interlaced data and method of operation

Details Memory cache with interlaced data and method of operation Memory cache with interlaced data and method of operation

1994-07-05

1996-03-12

Nelms, David C.

Static information storage and retrieval

Associative memories

Ferroelectric cell

36523001, 36518902, 395375, 395427, G11C 1500

Patent

active

054992044

ABSTRACT:
A memory cache (14) has a plurality of cache lines (50) for storing a series of contiguous memory elements. Each series of memory elements are interlaced within the corresponding cache line on a element-by-element basis and on a bit-by-bit basis. This storage strategy allows the memory cache to output a subset memory elements within a cache line quickly and in the original contiguous order. The invention may be advantageously incorporated in an instruction cache of superscalar data processor to provide a series of sequential instructions for execution.

REFERENCES:
patent: 4313158 (1982-01-01), Porter et al.
patent: 4933835 (1990-06-01), Sachs et al.
patent: 5313613 (1994-05-01), Gregor

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