Memory buffering with fast packet information access for a...

Details Memory buffering with fast packet information access for a... Memory buffering with fast packet information access for a...

2011-05-17

2011-05-17

Harper, Kevin C (Department: 2466)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S412000, C370S429000

Reexamination Certificate

active

07944930

ABSTRACT:
A networking device employing memory buffering in which a first memory is logically configured into blocks, and the blocks are logically configured into particles, where a second memory is configured to mirror the first memory in which a fixed number of bits in the second memory are allocated for each particle in the first memory so that scheduling and datagram lengths of packets stored in the first memory may be stored in the second memory. Other embodiments are described and claimed.

REFERENCES:
patent: 6799229 (2004-09-01), Lin
patent: 7050440 (2006-05-01), Colmant et al.
patent: 2003/0174699 (2003-09-01), Van Asten et al.
patent: 2005/0080953 (2005-04-01), Oner et al.
patent: 2007/0002863 (2007-01-01), Black
patent: 2007/0061693 (2007-03-01), Wickeraad
patent: 2007/0071034 (2007-03-01), Fleming
patent: 2007/0127480 (2007-06-01), Chen et al.

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