Memory buffer having selective flush capability

Details Memory buffer having selective flush capability Memory buffer having selective flush capability

1994-08-12

1995-05-23

Popek, Joseph A.

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

36518905, 365221, G11C 800

Patent

active

054187559

ABSTRACT:
A write buffer having selective flush is disclosed. The write buffer has address buffers and associated data buffers and comparators. During a "sneak read" operation, the address of the read operation is compared to the address signals stored in each of the address buffers. If a match is found, the read operation is temporarily suspended for only as long as the matched address remains stored in the write buffer. In a further improvement, the overhead associated with each match can be minimized to one write operation for each match before the matched address and data signals are written out of the write buffer.

REFERENCES:
patent: 5179679 (1993-01-01), Shoemaker
patent: 5276849 (1994-01-01), Patel
"Computer Architecture A Quantitative Approach", by John L. Hennessy and David A. Patterson, 1990, p. 458.
SPARClite User's Guide, Section 3.3 (2 pages) (1991).
LSI Logic L64815 MMU, Hot Chips 1991, p. 4.15.
DEC Alpha Chips, Hot Chips 1992, p. 1.16 (2 pages).
Intel i860, Hot Chips 1991, p. 3.17.
Ross HyperSparc, Hot Chips 1991, supplement.
Tera Microcore, Hot Chips 1991, p. 4.3.

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